why systemc? 
Author Message
 why systemc?

Hi, maybe you can help me:
I've been following the developments on systemc, and other high-level
languages for hardware modeling:
http://www.*-*-*.com/
http://www.*-*-*.com/
http://www.*-*-*.com/

*****

What is systemC? How is it different from other verification
languages?

Is SystemC compatible with System Verilog, Super log, or the like?

Are assertion based languages competing in the same space as SystemC?

What are the alternatives to SystemC when architecting/simulating
hardware systems?

Why would anyone bother to lear and use SystemC? Or, is it better to
wait for "wide acceptance" before spending time & effort on yet
another modeling language?

Thanks in advance for you feedback,

Alfredo.



Mon, 02 May 2005 04:55:19 GMT  
 why systemc?
Quote:

> What is systemC? How is it different from other verification
> languages?

1. SystemC is not a pure language as VHDL or Verilog or C/C++; it is
set of C++ class libraries. Its main purpose is description and simulation
of large systems where software and hardware coexist on equal terms.

Quote:
> Is SystemC compatible with System Verilog, Super log, or the like?

2. It is not, and it is good thing.
<swithing to sarcastic mode> System Verilog and Superlog are miserable
attempts to convert Verilog into something resembling normal programming
or hardware description language. Since Verilog camp zealots are totally
impervious to discussion based on issues, going any further here is pointless.
<back to regular mode>

Quote:
> Are assertion based languages competing in the same space as SystemC?

3. No, they have narrower scope than SystemC

Quote:
> What are the alternatives to SystemC when architecting/simulating
> hardware systems?

4. When it is pure hardware system (no embedded microcontrollers etc.)
you will do everything faster and more efficiently using VHDL or Verilog.
If your system contains RTOS (real time operating system) or any other
significant software part, SystemC saves a lot of time wasted on constant
translations between C descriptions and HDL descriptions. Plus, it is the
only solution that is close to standarization phase...

Quote:
> Why would anyone bother to lear and use SystemC? Or, is it better to
> wait for "wide acceptance" before spending time & effort on yet
> another modeling language?

5. If you are designing small to medium FPGAs you can skip SystemC for a
moment. If you are in large FPGA/ASIC designs, it is good idea to start
right now, because sooner or later SystemC is going to get you...

Some remarks after my personal experiences with SystemC:
I. On the PLUS side:
- you can get sources for SystemC for free, compile them using your C++
  compiler and you are ready to go
- testbench is necessary part of esch design, because what you get after
  final compilation is an executable you can run on your system
- if you have good C++ compiler, your simulation should be very fast
  (I have seen it on small designs, have not aquired/created large designs
   for verification of this statement yet.)
- if you have working knowledge of C/C++ and either VHDL or Verilog, you
  can write your first SystemC designs relatively fast
II. On the MINUS side:
- while installing and running SystemC on Unix/Linux is regular task,
  Windows users should beware: commercial C++ compilers have issues with
  SystemC. I have tried Microsoft and Borland and wrecked my nerves -
  switching to Cygwin/g++ finally worked...
- if you are using VHDL/Verilog on daily basis, you will be suprised
  how irritating some features of SystemC are for hardware descriptions:
  == switch statement accepts only inetger select expression anb choices
     (compare to case with vector expressions in HDLs)
  == bit-level access to vectors is possible only for variables, but not
     for ports and signals; simple task od splitting a bus or combining
     individual signals into a bus requires some heavy coding
  == ...
- majority of documentation for SystemC was written by system people
  for system people (chapter demonstrating SystemC coding for VHDL users
  in official manual is repository of most ridiculous coding styles).
  The only good book on SystemC for hardware people is "A SystemC Primer"
  by J. Bhasker - highly recommended!!!

Hope it helps,

Jerry



Tue, 03 May 2005 00:52:51 GMT  
 why systemc?
What about Verisity Specman?
--
Marty



Quote:
> > What is systemC? How is it different from other verification
> > languages?
> 1. SystemC is not a pure language as VHDL or Verilog or C/C++; it is
> set of C++ class libraries. Its main purpose is description and simulation
> of large systems where software and hardware coexist on equal terms.

> > Is SystemC compatible with System Verilog, Super log, or the like?
> 2. It is not, and it is good thing.
> <swithing to sarcastic mode> System Verilog and Superlog are miserable
> attempts to convert Verilog into something resembling normal programming
> or hardware description language. Since Verilog camp zealots are totally
> impervious to discussion based on issues, going any further here is
pointless.
> <back to regular mode>

> > Are assertion based languages competing in the same space as SystemC?
> 3. No, they have narrower scope than SystemC

> > What are the alternatives to SystemC when architecting/simulating
> > hardware systems?
> 4. When it is pure hardware system (no embedded microcontrollers etc.)
> you will do everything faster and more efficiently using VHDL or Verilog.
> If your system contains RTOS (real time operating system) or any other
> significant software part, SystemC saves a lot of time wasted on constant
> translations between C descriptions and HDL descriptions. Plus, it is the
> only solution that is close to standarization phase...

> > Why would anyone bother to lear and use SystemC? Or, is it better to
> > wait for "wide acceptance" before spending time & effort on yet
> > another modeling language?
> 5. If you are designing small to medium FPGAs you can skip SystemC for a
> moment. If you are in large FPGA/ASIC designs, it is good idea to start
> right now, because sooner or later SystemC is going to get you...

> Some remarks after my personal experiences with SystemC:
> I. On the PLUS side:
> - you can get sources for SystemC for free, compile them using your C++
>   compiler and you are ready to go
> - testbench is necessary part of esch design, because what you get after
>   final compilation is an executable you can run on your system
> - if you have good C++ compiler, your simulation should be very fast
>   (I have seen it on small designs, have not aquired/created large designs
>    for verification of this statement yet.)
> - if you have working knowledge of C/C++ and either VHDL or Verilog, you
>   can write your first SystemC designs relatively fast
> II. On the MINUS side:
> - while installing and running SystemC on Unix/Linux is regular task,
>   Windows users should beware: commercial C++ compilers have issues with
>   SystemC. I have tried Microsoft and Borland and wrecked my nerves -
>   switching to Cygwin/g++ finally worked...
> - if you are using VHDL/Verilog on daily basis, you will be suprised
>   how irritating some features of SystemC are for hardware descriptions:
>   == switch statement accepts only inetger select expression anb choices
>      (compare to case with vector expressions in HDLs)
>   == bit-level access to vectors is possible only for variables, but not
>      for ports and signals; simple task od splitting a bus or combining
>      individual signals into a bus requires some heavy coding
>   == ...
> - majority of documentation for SystemC was written by system people
>   for system people (chapter demonstrating SystemC coding for VHDL users
>   in official manual is repository of most ridiculous coding styles).
>   The only good book on SystemC for hardware people is "A SystemC Primer"
>   by J. Bhasker - highly recommended!!!

> Hope it helps,

> Jerry



Tue, 03 May 2005 01:19:00 GMT  
 why systemc?

Quote:


> > Is SystemC compatible with System Verilog, Super log, or the like?
> 2. It is not, and it is good thing.
> <swithing to sarcastic mode> System Verilog and Superlog are miserable
> attempts to convert Verilog into something resembling normal programming
> or hardware description language. Since Verilog camp zealots are totally
> impervious to discussion based on issues, going any further here is pointless.
> <back to regular mode>

Interesting how its SystemC and not SystemAda ...


Tue, 03 May 2005 17:47:40 GMT  
 why systemc?
I wanted to thank you ALL for your invaluable feedback.
These plus John Cooley's DAC report on SystemC have answered many questions.

Alfredo.



Tue, 10 May 2005 06:31:19 GMT  
 
 [ 5 post ] 

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