Verilog Model for Divider 
Author Message
 Verilog Model for Divider

Hi

I need the verilog model for 32 bit signed and unsigned multiplier.

Any help will be greatly appreciated.

Thanks

Gokhan Daglikoca



Sat, 02 Aug 2003 03:12:51 GMT  
 Verilog Model for Divider

I need the models for the divider sorry, not for the multiplier.

I am looking for the basic shiftr & substract method.

My problem is with aligning them MSB 1's of the dividend and the divisor
in 1 cycle. If this alignment is not done, in worst case the division
will take 2^32 cycles.

Thank you

Gokhan

Quote:

> Hi

> I need the verilog model for 32 bit signed and unsigned multiplier.

> Any help will be greatly appreciated.

> Thanks

> Gokhan Daglikoca



Sat, 02 Aug 2003 03:26:56 GMT  
 
 [ 2 post ] 

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