Gray Code Counter - Comments? 
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 Gray Code Counter - Comments?

// Someone in the VHDL newsgroup posted a question about doing a
//  Gray code counter, kind of an odd thing to ask for, but I thought
//  I'd give it a try in Verilog. This one works for up to 3 bit wide
//  inputs, to make it work for larger inputs just means a lot more
//  typing.
// Anyone have any comments about this coding style?
// I'm aware that converting to binary, using the Verilog add operation,
then
//  converting back to Gray is a lot less typing, but I don't know that
it
//  would synthesize very nicely. For this design and 3 bit wide inputs,
//  it fits into 6 Xilinx CLBs.
// Ken Coffman 4/27/98

module gray_add (clk, reset, gray1, gray2, gray_sum);
        parameter reg_size  =   3;          // Define default register size.
        input   clk;                        // Clock input.
        input   reset;                      // Reset input.
        input   [reg_size - 1: 0] gray1;    // First value to be added.
        input   [reg_size - 1: 0] gray2;    // Second value to be added.
        output  [reg_size:0] gray_sum;      // Result register, must be 1
larger than input size.
        reg     [reg_size:0] gray_sum;


                begin
                        if (reset)
                        begin
                        gray_sum <= 0;
                        end
                else case
   ({gray1, gray2})
    {3'h0 , 3'h0}    : gray_sum <= 4'h0;
    {3'h0 , 3'h1}    : gray_sum <= 4'h1;
    {3'h0 , 3'h3}    : gray_sum <= 4'h3;
    {3'h0 , 3'h2}    : gray_sum <= 4'h2;
    {3'h0 , 3'h6}    : gray_sum <= 4'h6;
    {3'h0 , 3'h7}    : gray_sum <= 4'h7;
    {3'h0 , 3'h5}    : gray_sum <= 4'h5;
    {3'h0 , 3'h4}    : gray_sum <= 4'h4;

    {3'h1 , 3'h0}    : gray_sum <= 4'h1;
    {3'h1 , 3'h1}    : gray_sum <= 4'h3;
    {3'h1 , 3'h3}    : gray_sum <= 4'h2;
    {3'h1 , 3'h2}    : gray_sum <= 4'h6;
    {3'h1 , 3'h6}    : gray_sum <= 4'h7;
    {3'h1 , 3'h7}    : gray_sum <= 4'h5;
    {3'h1 , 3'h5}    : gray_sum <= 4'h4;
    {3'h1 , 3'h4}    : gray_sum <= 4'hc;

    {3'h3 , 3'h0}    : gray_sum <= 4'h3;
    {3'h3 , 3'h1}    : gray_sum <= 4'h2;
    {3'h3 , 3'h3}    : gray_sum <= 4'h6;
    {3'h3 , 3'h2}    : gray_sum <= 4'h7;
    {3'h3 , 3'h6}    : gray_sum <= 4'h5;
    {3'h3 , 3'h7}    : gray_sum <= 4'h4;
    {3'h3 , 3'h5}    : gray_sum <= 4'hc;
    {3'h3 , 3'h4}    : gray_sum <= 4'hd;

    {3'h2 , 3'h0}    : gray_sum <= 4'h2;
    {3'h2 , 3'h1}    : gray_sum <= 4'h6;
    {3'h2 , 3'h3}    : gray_sum <= 4'h7;
    {3'h2 , 3'h2}    : gray_sum <= 4'h5;
    {3'h2 , 3'h6}    : gray_sum <= 4'h4;
    {3'h2 , 3'h7}    : gray_sum <= 4'hc;
    {3'h2 , 3'h5}    : gray_sum <= 4'hd;
    {3'h2 , 3'h4}    : gray_sum <= 4'hf;

    {3'h6 , 3'h0}    : gray_sum <= 4'h6;
    {3'h6 , 3'h1}    : gray_sum <= 4'h7;
    {3'h6 , 3'h3}    : gray_sum <= 4'h5;
    {3'h6 , 3'h2}    : gray_sum <= 4'h4;
    {3'h6 , 3'h6}    : gray_sum <= 4'hc;
    {3'h6 , 3'h7}    : gray_sum <= 4'hd;
    {3'h6 , 3'h5}    : gray_sum <= 4'hf;
    {3'h6 , 3'h4}    : gray_sum <= 4'he;

    {3'h7 , 3'h0}    : gray_sum <= 4'h7;
    {3'h7 , 3'h1}    : gray_sum <= 4'h5;
    {3'h7 , 3'h3}    : gray_sum <= 4'h4;
    {3'h7 , 3'h2}    : gray_sum <= 4'hc;
    {3'h7 , 3'h6}    : gray_sum <= 4'hd;
    {3'h7 , 3'h7}    : gray_sum <= 4'hf;
    {3'h7 , 3'h5}    : gray_sum <= 4'he;
    {3'h7 , 3'h4}    : gray_sum <= 4'ha;

    {3'h5 , 3'h0}    : gray_sum <= 4'h5;
    {3'h5 , 3'h1}    : gray_sum <= 4'h4;
    {3'h5 , 3'h3}    : gray_sum <= 4'hc;
    {3'h5 , 3'h2}    : gray_sum <= 4'hd;
    {3'h5 , 3'h6}    : gray_sum <= 4'hf;
    {3'h5 , 3'h7}    : gray_sum <= 4'he;
    {3'h5 , 3'h5}    : gray_sum <= 4'ha;
    {3'h5 , 3'h4}    : gray_sum <= 4'hb;

    {3'h4 , 3'h0}    : gray_sum <= 4'h4;
    {3'h4 , 3'h1}    : gray_sum <= 4'hc;
    {3'h4 , 3'h3}    : gray_sum <= 4'hd;
    {3'h4 , 3'h2}    : gray_sum <= 4'hf;
    {3'h4 , 3'h6}    : gray_sum <= 4'he;
    {3'h4 , 3'h7}    : gray_sum <= 4'ha;
    {3'h4 , 3'h5}    : gray_sum <= 4'hb;
    {3'h4 , 3'h4}    : gray_sum <= 4'h9;

                default:    gray_sum <= 0;

                endcase
        end
        endmodule



Fri, 13 Oct 2000 03:00:00 GMT  
 Gray Code Counter - Comments?

Quote:

> // Someone in the VHDL newsgroup posted a question about doing a
> //  Gray code counter, kind of an odd thing to ask for, but I thought

                ^^^^^^^

I guess you mean adder?

Quote:
> //  I'd give it a try in Verilog. This one works for up to 3 bit wide
> //  inputs, to make it work for larger inputs just means a lot more
> //  typing.
> // Anyone have any comments about this coding style?
> // I'm aware that converting to binary, using the Verilog add operation,
> then
> //  converting back to Gray is a lot less typing, but I don't know that
> it
> //  would synthesize very nicely. For this design and 3 bit wide inputs,
> //  it fits into 6 Xilinx CLBs.
> // Ken Coffman 4/27/98

[...snip... code to implement gray code adder deleted]

I once wrote a C program to generate a case statement to implement
several Gray Code Counters. I guess you could save yourself some
typing and mistyping if you write a program/script to generate the
code. There's currently a discussion on gray code adders in comp.arch.

Petter
--
________________________________________________________________________
Petter Gustad     8'h2B | (~8'h2B) - Hamlet     http://home.sol.no/~pegu
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("pegu\100computer\056org\nmy opinions only\n");}



Sat, 14 Oct 2000 03:00:00 GMT  
 
 [ 2 post ] 

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