vcs compile and verilog coding 
Author Message
 vcs compile and verilog coding

Hi verilog users,

I am working on somebody elses code and using vcs and verilog-xl.
Now vcs is a faster simulator by far but for some strange reason,
it insists on re compiling each and every module. It also doesn't
help that a lot of files are "include"d and HAVE to be compiled, and
some half-hearted attempts by me to change the structure was duely
rejected by vcs.

Well, the result is that the compilation for vcs takes SOOO much time,
it is easier and faster for me to run verilog-xl.

Does someone know how to keep the dependencies separate so that only
changed files will be recompiled. e.g. how to have tasks in a separate
file and compile as a separate object file instead of including into`the
module. I have worked in c/make extensively, and am comfortable and like
the way I can take care of dependencies in an efficient manner.

Any advice is very much appreciated

Kaustabh

--


Opinions expressed here are my own
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Kaustabh Duorah
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Sat, 22 Jan 2000 03:00:00 GMT  
 vcs compile and verilog coding

Quote:

> Hi verilog users,

> I am working on somebody elses code and using vcs and verilog-xl.
> Now vcs is a faster simulator by far but for some strange reason,
> it insists on re compiling each and every module.
...
> Does someone know how to keep the dependencies separate so that only
> changed files will be recompiled. e.g. how to have tasks in a separate

...

Perhaps I'm over simplifying, but do you have incremental compile
turned on?  It is a command line option and I don't believe it is
the default even with the latest version of vcs.

--

Chandler, Arizona, USA



Wed, 26 Jan 2000 03:00:00 GMT  
 
 [ 2 post ] 

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