simple verilog question 
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 simple verilog question

Consider the 2 statements:



a2 should change one cycle later than a1.
Both changed same time when delay1 == delay2.
Fix was to make delay1 > delay2.
This seems counter intutive. Can anyone explain
how things get executed.

Thanks

vm



Tue, 20 May 1997 04:57:17 GMT  
 simple verilog question
: Consider the 2 statements:



:  
: a2 should change one cycle later than a1.
: Both changed same time when delay1 == delay2.
: Fix was to make delay1 > delay2.
: This seems counter intutive. Can anyone explain
: how things get executed.

These two statements are being executed in parallel. On the rising edge of
clk, both of the statements are activated. When delay1 == delay2, both
of the assignments will also take place within the same time unit.

To have a2 change one cycle later than a1, the code would look like:


begin
 #delay1 a1 = a ;

end

This will work unless delay1 & delay2 >= clk period.

: Thanks

: vm

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Mon, 26 May 1997 03:00:51 GMT  
 simple verilog question

Quote:

>Consider the 2 statements:



>a2 should change one cycle later than a1.
>Both changed same time when delay1 == delay2.
>Fix was to make delay1 > delay2.
>This seems counter intutive. Can anyone explain
>how things get executed.

>Thanks

>vm

If you write:



,then the value on the right side of the expression will be sampled on the edge
of the clock exactly, but will only "appear" on the left-side after delay1/2.
a2 will contain what a1 contains now, one clock edge and #delay2 later. In this
example, the relation between delay1 and delay2 does not matter, i.e.  they can
be anything, provided they are less than the clock period, or else! In your
example, relation between delay1 and delay2 matters, because depending on the
sign of delay1 - delay2, the first or second statement will complete ahead of
the other. If delay1 = delay2 you are in worse trouble, as it is the simulator
that decides the order of events for you (you don't want that!).

Cheers,

Frank Ieromnimon
PACE Research Project,
Essex University.



Tue, 27 May 1997 03:09:06 GMT  
 
 [ 3 post ] 

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