UDP help requested 
Author Message
 UDP help requested

Hello!

Could someone wise in the ways of science explain why this perfectly
good UDP isn't working?

module test;
    reg      x1;
    reg      x2;

    c_element  cinst(y, x1, x2);

    initial begin
                $monitor($realtime,"  x1=%b  x2=%b  y=%b",x1,x2,y);
                x1=1; x2=1;
                #10 x1=1; x2=0;
                #10 x1=0; x2=1;
                #10 x1=0; x2=0;
                #10 x1=1; x2=0;
                #10 x1=0; x2=1;
                #10 x1=0; x2=0;
                #10 $stop;
    end

endmodule

primitive c_element(y, x1, x2);

    output  y;
    input   x1, x2;

    reg y;

    table
    // x1  x2  :  y- : y+

       1  1    :  ?  : 1;
       0  0    :  ?  : 0;

       0  1    :  ?  : -;
       1  0    :  ?  : -;

    endtable
endprimitive

FOR AN OUTPUT I GET THIS:

Compiling source file "check_celem.v"
GRAPHICS  4.3 Mon Nov 1 19:53:44 PST 1993 (cmrd1)
Highest level modules:
test

0  x1=1  x2=1  y=1
10  x1=1  x2=0  y=1
20  x1=0  x2=1  y=1
30  x1=0  x2=0  y=0
40  x1=1  x2=0  y=0
50  x1=0  x2=1  y=1
60  x1=0  x2=0  y=0
L23 "check_celem.v": $stop at simulation time 700

At time 50 y->1 when it should stay at 0!?

This is my first stab at UDP's please forgive my naivete'

regards,



Sat, 28 Sep 1996 05:35:41 GMT  
 UDP help requested
|> Hello!
|>
|> Could someone wise in the ways of science explain why this perfectly
|> good UDP isn't working?
|> [testbed deleted]
|>
|> primitive c_element(y, x1, x2);
|>
|>     output  y;
|>     input   x1, x2;
|>
|>     reg y;
|>
|>     table
|>     // x1  x2  :  y- : y+
|>
|>        1  1    :  ?  : 1;
|>        0  0    :  ?  : 0;
|>
|>        0  1    :  ?  : -;
|>        1  0    :  ?  : -;
|>
|>     endtable
|> endprimitive
|>

Your UDP is working fine. This is a good example of a race condition.

It is impossible for two inputs to a device to change at EXACTLY the
same time. In your case, the UDP sees X2 going to 1 before seeing X1
going to 0. In that brief instant x1 and x2 are 1, y->1. You have to
assume that a gate gets evaluated once per input change, and you can't
assume any order to the gate evaluation.

--
___________________________________________________________

Cadence Design, 270 Billerica Rd., Chelmsford MA 01824-4140
"I used to have Time. Now I have Twins"
___________________________________________________________



Sat, 28 Sep 1996 23:57:04 GMT  
 UDP help requested

| Hello!
|
| Could someone wise in the ways of science explain why this perfectly
| good UDP isn't working?
|
    initial begin
                $monitor($realtime,"  x1=%b  x2=%b  y=%b",x1,x2,y);
                x1=1; x2=1;
                #10 x1=1; x2=0;
                #10 x1=0; x2=1;
                #10 x1=0; x2=0;
                #10 x1=1; x2=0;
                #10 x1=0; x2=1;
                #10 x1=0; x2=0;
                #10 $stop;
    end
endmodule

primitive c_element(y, x1, x2);
    output  y;
    input   x1, x2;
    reg y;
    table
    // x1  x2  :  y- : y+
       1  1    :  ?  : 1;
       0  0    :  ?  : 0;
       0  1    :  ?  : -;
       1  0    :  ?  : -;
    endtable
endprimitive

|
| Compiling source file "check_celem.v"
| GRAPHICS  4.3 Mon Nov 1 19:53:44 PST 1993 (cmrd1)
| Highest level modules:
| test
|
|  0  x1=1  x2=1  y=1
| 10  x1=1  x2=0  y=1
| 20  x1=0  x2=1  y=1
| 30  x1=0  x2=0  y=0
| 40  x1=1  x2=0  y=0
| 50  x1=0  x2=1  y=1
| 60  x1=0  x2=0  y=0
| L23 "check_celem.v": $stop at simulation time 700
|
| At time 50 y->1 when it should stay at 0!?
|
| This is my first stab at UDP's please forgive my naivete'
|
| regards,

        You have a race.  At time 50, you have two signals changing
simultaneously. x1 is going from 1->0, and x2 is going from 0->1.
Verilog-XL has an accelerate option (-a I believe) that will alter the
behaviour here.  In the transistion, it is possible that x2 may have
gone to 1 before x1 went to zero.  This gets you to your x1=1,x2=1 =>
y=1 state.  Then you get to the x1=0,x2=1, y=>y, which holds this new
value.
        You have another transistion from {x1,x2} 10 -> 01, at time
20, however in this case y is already 1, so you don't see the false
toggle.

        Running your test on VCS, we don't see the problem. I'll bet
you if you turn off the -a option to Verilog-XL if it is on, or turn
it on if it is off, the test will behave differently.

% vcs plim.v
% simv
Contains Chronologic Simulation proprietary information.  Apr 12 08:47 1994

 0  x1=1  x2=1  y=1
10  x1=1  x2=0  y=1
20  x1=0  x2=1  y=1
30  x1=0  x2=0  y=0
40  x1=1  x2=0  y=0
50  x1=0  x2=1  y=0
60  x1=0  x2=0  y=0
$stop at simulation time 70
C1 > $finish at simulation time                   70
           V C S   S i m u l a t i o n   R e p o r t
Time: 70
CPU Time:   0.050 seconds; Data structure size: 0.0Mb
Tue Apr 12 08:47:34 1994

--


`------'                          For information, call 1-800-VERILOG



Sun, 29 Sep 1996 00:01:39 GMT  
 UDP help requested
You have a race condition. For an infinitesimal period of time between
{x1,x2} = 'b10 and {x1,x2} = 'b01, {x1,x2} = 'b11! ( depending on which
event, x1 or x2, occurs first )

We just had a big discussion about the undesirability of race conditions,
and the undesirability of defining event order within the semantics.
Remarks were also made about how nice it would be to have a tool that
statically found race conditions in code ( dynamically would be OK too,
as long as it doesn't permanently damage simulation performance ).

                                                John Williams



Sun, 29 Sep 1996 14:24:50 GMT  
 
 [ 4 post ] 

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