question about reg and wire types
Hi,
Sounds like perfect Verilog code to me, I just tested the following
simple code on Modelsim and it works fine. Did you face any issues
with such a code?
Ajeetha,
http://www.noveldv.com
// code..
module dut (a,b);
output [15:0] a;
input [7:0] b;
assign a = { b, x};
initial
$monitor ($time," %m Value of b %b x %b a %b",b,x,a);
endmodule // dut
module tb_dut ();
wire [15:0] a;
reg [7:0] b;
reg [7:0] x;
dut d0 (a,b);
initial
begin
b <= 8'd14;
#5 b <= 8'd12;
#10 b <= 8'd22;
end
assign d0.x = x;
initial
begin
x <= 8'd14;
#5 x <= 8'd12;
#10 x <= 8'd22;
end
endmodule // tb_dut
Quote:
> If I have an internal reg variable x[7:0] and a input port y[7:0], and
> an output port port[15:0]
> Is this a legal verilog assignment:
> assign port = {x,y};
> If it is legal verilog, are there some simulators that mess this up,
> like Modelsim? Thanks.
