Widman Associates Training-Verilog/Synthesis-Language Classes-ON-Sites At your Location.... 
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 Widman Associates Training-Verilog/Synthesis-Language Classes-ON-Sites At your Location....

WIDMAN ASSOCIATES

                     HARDWARE DESCRIPTION LANGUAGE
                                    AND SYNTHESIS
                            METHODOLOGY TRAINING

                                         VERILOG

                                           VHDL

                                        VERILOG VS. VHDL

                                  DESIGN FOR SYNTHESIS
                                       (Verilog or VHDL)

What are Language Training Classes:

Language Training Courses are one to four days
long and will get you on track to creating top-down
designs using VHDL, Verilog, and Synthesis. These
are language and methodology classes taught by
designers for designers.

Design for Synthesis
         Summary:

This course answers the questions: "How do I complete
a design effectively using a "HDL" and synthesis?" It does
this by focusing on a methodology that uses a single HDL
design that keeps simulation, synthesis, and test all in
mind.

Topics include: what is synthesis, how it effects your design
methodology, converting of structured-behavi{*filter*}HDL to gates, how to
control and manage the design and tool to get
what you expect, performance issues, style guidelines, libraries and much
more.

This class is taught using Verilog -HDL- or VHDL and Synopsis
synthesis.

                               VERILOG OR VHDL
                                   SUMMARY

These two classes focus on the complete HDL language. Emphasis is on using
the language for getting designs
done efficiently.

These courses not only teach the language basics, but also cover design
and test style, performance and portability issues, timing methodology,
and introduction to synthesis, and tell you where you can get additional
information.

You can pick the tool and the course may be tuned for your specific needs
in both emphasis and length.

Pre-requisites:  Some design, simulation, or programming experience
helpful.

Simulators Available: Model Technology, Synopsis, Mentor Graphics and
Others.

Verilog: Cadence, Chronologic, and Frontline.

Course Length: 3-4 days, 55% lecture and 45% lab.

---------------------------------------------------

Why do customers keep coming back to Widman Associates
for their training needs?

*Focus is on using the language for design rather than the
tool.

*  Instructors are very experienced in both Design and CAE.

* Detailed Understanding of Verilog, VHDL, and Synthesis.

*  Experience with most EDA Vendor Tools.

*  Outstanding material tuned by feedback from over
thirty different customers.

*  Class material that becomes a thorough reference guide
when the student has completed the course.

* An "unbiased" perspective of the use of the languages.

What do our Customers Say About our Training:

"... the presentation material, depth of understanding, and
instructors excellent communication skills make the concepts
and technology potential readily understandable by all".

"By far the most comprehensive comparison between Verilog and VHDL that I
have ever seen".

"I liked everything, especially the real world examples, methodology, and
performance info".

"I liked the interactivety of the class and the ability of the
instructor to answer all questions on both HDL languages
and synthesis."

----------------------------------------------------

To receive more information on Widman Associates
Training Classes, please contact: Suzanne Southworth,




Fri, 02 May 1997 09:40:22 GMT  
 
 [ 1 post ] 

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