Textio in Verilog 
Author Message
 Textio in Verilog

Hi,

I am a very confident user of VHDL. See my answers in comp.lang.vhdl.
I need to write a testbench
in Verilog for a received netlist.
Are there similar packages in Verilog like the textio package in VHDL ?

I want to read data in from a file and use this data as a simulation
testbench.
Any ideas ?

Regards

Braam Greyling



Mon, 10 Dec 2001 03:00:00 GMT  
 Textio in Verilog
You'll need the PLI...try this:

http://www.chris.spear.net/pli/fileio.htm

/Ed

Quote:

> I am a very confident user of VHDL. See my answers in comp.lang.vhdl.
> I need to write a testbench
> in Verilog for a received netlist.
> Are there similar packages in Verilog like the textio package in VHDL ?

> I want to read data in from a file and use this data as a simulation
> testbench.
> Any ideas ?

--



Mon, 10 Dec 2001 03:00:00 GMT  
 Textio in Verilog

Quote:

>I am a very confident user of VHDL. See my answers in comp.lang.vhdl.
>I need to write a testbench
>in Verilog for a received netlist.
>Are there similar packages in Verilog like the textio package in VHDL ?

Have you considered using the "Plus" variant of ModelSim from Model
Technology and writing your testbench in VHDL while simulating the
Verilog netlist?

If doing VHDL, there's a high probability you already have ModelSim
but might need another license for the Verilog side. Probably worth it
as if you know what you want from VHDL you can get the job done now,
rather than learning a new load of tools and language.

Cheers
Stuart
An employee of Saros Technology:
Model Technology, Exemplar Logic, TransEDA, Renoir.
www.saros.co.uk



Mon, 10 Dec 2001 03:00:00 GMT  
 Textio in Verilog

Quote:

> Hi,

> I am a very confident user of VHDL. See my answers in comp.lang.vhdl.

.. cut..

Edward is right with PLI, but ... if you just want to stimulate your
circuit
from a file holding your values you could use readmemb as well.

If necessary I could send you an examle

Frank



Tue, 11 Dec 2001 03:00:00 GMT  
 Textio in Verilog
Frank,

Thanks very much.

I have a book for Verilog but if you can send me an example for readmemb,
it wont do any damage !

Thanks for the answer.

Regards

Braam

Quote:


> > Hi,

> > I am a very confident user of VHDL. See my answers in comp.lang.vhdl.

> .. cut..

> Edward is right with PLI, but ... if you just want to stimulate your
> circuit
> from a file holding your values you could use readmemb as well.

> If necessary I could send you an examle

> Frank



Fri, 14 Dec 2001 03:00:00 GMT  
 Textio in Verilog
Stuart,

Thanks very much for the answer.
Unfortunately my chip manufacturer only has access to Verilog.
Regards

Braam Greyling

Quote:

> Have you considered using the "Plus" variant of ModelSim from Model
> Technology and writing your testbench in VHDL while simulating the
> Verilog netlist?



Fri, 14 Dec 2001 03:00:00 GMT  
 
 [ 6 post ] 

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