verilog vs VHDL 
Author Message
 verilog vs VHDL

What is more widely used: VHDL or verilog?

Why?

IS there an equalivant to PLIs in VHDL? Does VHDL have something
that verilog doesn't have?

Just wondering,
Joe



Tue, 16 Dec 2003 11:04:13 GMT  
 verilog vs VHDL
I think you will find that in America, Verilog is preferred, but in Europe
VHDL is the one.  Not sure why it is so, but this is what I have heard.  As
for which is better, its like a holy war (both sides completely convinced
they have the only answer), so I don't need to get into it, except to say
that VHDL is a more powerful language than Verilog, but with that power
comes some baggage.  Lots of designers have decided that if they don't need
the extra power, then the trade for a leaner language makes sense (quicker
simulations, primarily).


Quote:
> What is more widely used: VHDL or verilog?

> Why?

> IS there an equalivant to PLIs in VHDL? Does VHDL have something
> that verilog doesn't have?

> Just wondering,
> Joe



Tue, 16 Dec 2003 21:00:39 GMT  
 verilog vs VHDL

Quote:

> What is more widely used: VHDL or verilog?

Depends on who you ask.

Quote:
> IS there an equalivant to PLIs in VHDL? Does VHDL have something
> that verilog doesn't have?

VHDL has:
* stronger file i/o support (without PLI) [both languages need much
stronger file i/o support, imho]

* strong typing, so the compiler catches your stupid mistakes/typos, not
your logic analyzer

* generate

* configurations

* generics that make sense

* an EXCELLENT emacs mode

Verilog users always say that "VHDL is verbose -- you have to type a
lot."  So, in Verilog, why must I, when typing in my new module:

a) enter the list of I/O:

module mymod (in1, in2, in3, in4, out1, out2, out3);

b) THEN indicate whether it's input or output, and vector size

        input in1, in2;
        input [3:0] in3, in4;
        output out1, out2, out3;

(This is all very much like the deprecated K&R C style.)

c) THEN indicate whether the things are regs or wires:

        wire out1, out2;
        reg out3;

Lots of typing there.

there's more, but I grow weary.
-andy



Wed, 17 Dec 2003 01:02:04 GMT  
 verilog vs VHDL

Quote:
> there's more, but I grow weary.
> -andy

Andy,
    Don't grow weary!  Try Gretal C, the new and improved sister of Handel
C.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA


Wed, 17 Dec 2003 20:07:52 GMT  
 verilog vs VHDL


Quote:
>    Don't grow weary!  Try Gretal C, the new and improved sister of Handel
>C.

C'mon, tell us more!  A quick Google search for "handel gretal" and
then "synchronous design gretal" yielded nothing even though
looking for "handel c" turns up all the usual suspects...
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
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from  your  system, any  use, disclosure, or copying  of this  document  is
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are not the views of Doulos Ltd., unless specifically stated.



Fri, 19 Dec 2003 18:01:51 GMT  
 verilog vs VHDL


Quote:
>Verilog users always say that "VHDL is verbose -- you have to type a
>lot."  So, in Verilog, why must I, when typing in my new module:

>a) enter the list of I/O:

>module mymod (in1, in2, in3, in4, out1, out2, out3);

>b) THEN indicate whether it's input or output, and vector size

>       input in1, in2;
>       input [3:0] in3, in4;
>       output out1, out2, out3;

>(This is all very much like the deprecated K&R C style.)

>c) THEN indicate whether the things are regs or wires:

>       wire out1, out2;
>       reg out3;

Well, EDA tools tend to lag about a decade behind software tools;
K&R C is vintage mid-70s, Verilog is vintage mid-80s, so no
surprises there.

HOWEVER, I've said this before and I'll doubtless say it again,
but I fervently believe it's worth saying until folks get around
to listening:
BEAT UP YOUR TOOL VENDORS UNTIL THEY START SUPPORTING ALL THE
NEW VERILOG-2000 (2001?) FEATURES.  Then you'll be able to write

  module (
    input in1,
    output reg [3:0] out1,
    output wire out2
  );

and a whole load of other things that are even more important.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Fri, 19 Dec 2003 18:10:24 GMT  
 verilog vs VHDL
Quote:
> >    Don't grow weary!  Try Gretal C, the new and improved sister of
Handel
> >C.

> C'mon, tell us more!  A quick Google search for "handel gretal" and
> then "synchronous design gretal" yielded nothing even though
> looking for "handel c" turns up all the usual suspects...
> --
> Jonathan Bromley
> DOULOS Ltd.
> Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United
Kingdom
> Tel: +44 1425 471223                     Email:


Quote:
> Fax: +44 1425 471573                             Web:

http://www.doulos.com

Jonathan,
     Sorry to have led you on a wild goose chase.  IT WAS A JOKE!
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA



Sat, 20 Dec 2003 01:15:05 GMT  
 verilog vs VHDL


Quote:
>> >    Don't grow weary!  Try Gretal C, the new and improved sister of
>> >    Handel-C.
>Jonathan,
>     Sorry to have led you on a wild goose chase.  IT WAS A JOKE!

Oh dear me.  Normally I reckon to be less gullible than that.
Must've been having an off day....

Quite a good joke really.

Sadly there is a precedent for taking this all too seriously... there
once was a derivative of Handel-C called Bach.

Cheers,
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Sat, 20 Dec 2003 01:28:41 GMT  
 verilog vs VHDL

Quote:
> Well, EDA tools tend to lag about a decade behind software tools;
> K&R C is vintage mid-70s, Verilog is vintage mid-80s, so no
> surprises there.

> HOWEVER, I've said this before and I'll doubtless say it again,
> but I fervently believe it's worth saying until folks get around
> to listening:
> BEAT UP YOUR TOOL VENDORS UNTIL THEY START SUPPORTING ALL THE
> NEW VERILOG-2000 (2001?) FEATURES.  Then you'll be able to write

>   module (
>     input in1,
>     output reg [3:0] out1,
>     output wire out2
>   );

> and a whole load of other things that are even more important.
> --
> Jonathan Bromley
> DOULOS Ltd.

Jonathan,
     Do us all a favor and post any inklings on this Verilog 2000/2001
stuff.  We will all appreciate it (unless of course this is also a joke!).
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA


Sat, 20 Dec 2003 05:02:20 GMT  
 verilog vs VHDL


Quote:
>Jonathan,
>     Do us all a favor and post any inklings on this Verilog 2000/2001
>stuff.  We will all appreciate it (unless of course this is also a joke!).

No joke, at least not until all the tool vendors decide they are not
going to bother to support it :-(

As I understand it the standard is fully ratified and on the point of
being published (end of this month??);  meanwhile, Stuart Sutherland
has an excellent presentation on the key changes, albeit with a few
details frustratingly missing, and other useful stuff at

http://www.verilog-2001.com/
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Sat, 20 Dec 2003 16:09:08 GMT  
 verilog vs VHDL

Quote:
> As I understand it the standard is fully ratified and on the point of
> being published (end of this month??);  meanwhile, Stuart Sutherland
> has an excellent presentation on the key changes, albeit with a few
> details frustratingly missing, and other useful stuff at
> Jonathan Bromley

     It sounds like the standard is fully "rarified!"
     Thanks for the update.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA


Sat, 20 Dec 2003 20:43:19 GMT  
 verilog vs VHDL
Maybe you'll find an answer to the original question,
"Can someone point out semantic differences between VHDL and verilog?
Possibly how is simulating designs is different for VHDL and verilog
?"

in the book "HDL Chip Design, A practical Guide for Designing,
Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog"
(ISBN 0-9651934-3-8).

I found this book very handy in my work. It's full of example and on
every other page it puts VHDL and Verilog code side by side for
comparison.

/Andreas



Sun, 21 Dec 2003 22:31:38 GMT  
 verilog vs VHDL
Also, VHDL has libraries, packages, overloaded functions and operators, and
local storage within functions.

--





Quote:

> > What is more widely used: VHDL or verilog?

> Depends on who you ask.

> > IS there an equalivant to PLIs in VHDL? Does VHDL have something
> > that verilog doesn't have?

> VHDL has:
> * stronger file i/o support (without PLI) [both languages need much
> stronger file i/o support, imho]

> * strong typing, so the compiler catches your stupid mistakes/typos, not
> your logic analyzer

> * generate

> * configurations

> * generics that make sense

> * an EXCELLENT emacs mode

> Verilog users always say that "VHDL is verbose -- you have to type a
> lot."  So, in Verilog, why must I, when typing in my new module:

> a) enter the list of I/O:

> module mymod (in1, in2, in3, in4, out1, out2, out3);

> b) THEN indicate whether it's input or output, and vector size

> input in1, in2;
> input [3:0] in3, in4;
> output out1, out2, out3;

> (This is all very much like the deprecated K&R C style.)

> c) THEN indicate whether the things are regs or wires:

> wire out1, out2;
> reg out3;

> Lots of typing there.

> there's more, but I grow weary.
> -andy



Wed, 24 Dec 2003 01:32:45 GMT  
 
 [ 13 post ] 

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