Verilog vs VHDL Syntax comparison 
Author Message
 Verilog vs VHDL Syntax comparison

Hi all,

I need to convert a VHDL fully behavioural model in Verilog (behav
again); I don't want to use any automatic conversion tool, though: the
code is not so long, and It takes maybe less time to do it by hand
rather than let a tool do it and then correct the result...
furthermore, I want to use it as a useful verilog exercise.

Does anybody have a link to a comparative table for the syntax of the
two languages, to be used as a reference?



Sat, 28 Feb 2004 19:44:13 GMT  
 Verilog vs VHDL Syntax comparison


> Hi  Stefano,
> Have a look at the actel website. which gives side by side examples of
> vhdl and verilog. I found it very useful.

> Sanjay

Another good source of side-by-side examples is the book by Douglas

HDL Chip Design, Doone Publications, ISBN 0-9651934-3-8

Focuses on synthesisable code mainly but has some really nice bits about
"bad" code.

Sun, 29 Feb 2004 07:33:46 GMT  
 Verilog vs VHDL Syntax comparison

A comparison was done in the form of a design article in EDN access.
Here is the url.
Hope this helps as for the verilog/VHDL porting.


Wed, 03 Mar 2004 07:25:27 GMT  
 [ 3 post ] 

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