parameter redefinition 
Author Message
 parameter redefinition

Hello,

I am looking for a means of redefining parameters such that
multiple instantiations of similar modules can be had with different
characteristics, without having to recompile the model (or
compile separate models) for each use.

In particular, I'm trying to model a memory device that
will have different timing parameters according to its
voltage supply (5 or 3.3V).

One method of doing this, I suppose, would be by setting
flags (in this example vcc33):
module memory;
`ifdef vcc33
   `define tRAS 80
...
/* defaults */
`else
   `define tRAS 70
...
`endif

- however, this method means the code has to be rewritten
for each test in order to define/undefine (comment out) vcc33.  
It is hardcoded and has lost the flexability of parameters.

The solution I'm looking for would be something like:
module memory;
parameter VCC = 5,
...  
;
/* timing parameter defaults */
parameter
  tRAS = 70,
  ...
initial begin
  if(VCC==3.3) begin
    tRAS = 80;
    ...
  end
  ...
end

I've tried to do this with defparam commands but apparently
they must be outside of all blocks, and hence cannnot access the
parameters that would be used to determine which set of timing
parameters to use.

If you have any information, hints, solutions... any kind of
help please post to the group or drop me some email.

Thanks in advance,
Terence

--
_______________
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Hewlett-Packard (Canada) Ltd.

20 Lexington Rd.                         TEL (519) 883-3110
Waterloo, Ontario N2J-3Z3                FAX (519) 886-8620
CANADA



Mon, 30 Dec 1996 06:05:56 GMT  
 parameter redefinition
You can use a work around

1) create a script for example "./verilogShell"

        script: ./verilogShell
_____________________________________________________
#!bin/csh

rm ./definitions_file

echo \`define tRAS $1 > ./definitions_file
verilog -f ./definitions_file your_arguments

_____________________________________________________

2) Execute verilog:
                        prompt> ./verilogShell 80

Regards,        Yehoshua

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* ELLEMTEL Utv. AB      * ECN   851 3442                *
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Mon, 30 Dec 1996 11:36:17 GMT  
 parameter redefinition
Hello,

I am trying to write synthesizable code for the following:

reg A,B,C,D;
wire NA,reset,clk;

initial
  begin
    A = 0;
    B = 0;
    C = 1;
    D = 1;
  end

// some other code ..


  begin
    if (reset)
      A=1;
    else
      A=NA;
  end

// some other code

If there is an external RESET to the circuit, then I do not need
the initial statement. However, it is possible that there will
be no external RESET and I need to start with a particular value
(0 or 1) in the registers A,B,C,D.

My first question is : how can I change my code such that the above
code can be synthesized ? (Assuming an initial statement is not
supported by the Verilog synthesizer..)
Can this be done without an external RESET
input to a module which would contain code as above?

Secondly, approx. how many of the Verilog Synthesis Tools can handle
pullup and pulldown sources?

I am writing this at the end of the day, and am probably not thinking
straight..if any thing is unclear, pls. send me mail.

Thanks in advance,

--
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*       Alternative System Concepts, Inc.       *
*       PO Box 128 Windham NH 03087             *
*       tel (603) 437-2234 fax (603) 437-ASC2   *



Tue, 31 Dec 1996 05:48:22 GMT  
 parameter redefinition

Quote:

> ...
> module memory;
> `ifdef vcc33
>    `define tRAS 80
> ...
> /* defaults */
> `else
>    `define tRAS 70
> ...
> `endif

> - however, this method means the code has to be rewritten
> for each test in order to define/undefine (comment out) vcc33.  
> It is hardcoded and has lost the flexability of parameters.

Hardcoded is one way, but not the only way for the use of `ifdef.
When invoking verilog, without the "plus-parameter" +define+vcc33
on the command line or as long as textmacro vcc33 has not been defined
when those lines are compiled/interpreted, the tRAS (another textmacro)
will assume the value 70, otherwise, it will assume 80.

BTW, I think the tRAS should be a parameter (instead of a textmacro).
If you have several types of memories and they happen to have diff.
tRAS, then you'll have a lot of fun. :) In other words, this type
of coding style is potentially hazardous and thus will limit its
reusability.

Steven
--
"Life is a series of problems. ... Yet it is in this whole process of
meeting and solving problems that life has its meaning."
                       From "The Road Less Traveled" by M. Scott Peck



Mon, 30 Dec 1996 23:25:28 GMT  
 parameter redefinition

| Hello,
| I am looking for a means of redefining parameters such that
| multiple instantiations of similar modules can be had with different
| characteristics, without having to recompile the model module memory;
| parameter VCC = 5,
| ...  
| ;
| /* timing parameter defaults */
| parameter
|   tRAS = 70,
|   ...
| initial begin
|   if(VCC==3.3) begin
|     tRAS = 80;
|     ...
|   end
|   ...
| end

See section 12.2.2 of your OVI Verilog LRM, page 12-8.

Basically, define your memory module as:

module memcell(a,b);
        parameter dly = 1.0, size = 1;
        output [size-1:0] a;
        input [size-1:0] b;

        not #dly (a,b); // or what ever...

endmodule

Then instantiate it as:

module top;
    wire [3:0] o1;
    wire [6:0] o2;
    reg  [3:0] i1;
    reg  [6:0] i2;
// mem's instance m1 will have dly 3.2, size 4
    m1 #(3.2,4) mem(o1, i1);
// mem's instance m2 will have dly 2.7, size 7  
    m2 #(2.7,7) mem(o2, i2);

endmodule
--


`------' A VIEWlogic Company      For information, call 1-800-VERILOG



Tue, 31 Dec 1996 11:37:11 GMT  
 parameter redefinition

Quote:

>Hello,

>I am looking for a means of redefining parameters such that
>multiple instantiations of similar modules can be had with different
>characteristics, without having to recompile the model (or
>compile separate models) for each use.
>`ifdef vcc33
>   `define tRAS 80
>...
>/* defaults */
>`else
>   `define tRAS 70
>...
>`endif

In some simulators, particularly XL and VeriWell, you can use the +define
command line option to define vcc33.

e.g.

veriwell -f model.vc +define+vcc33

Hope this is what you were looking for.



Sun, 05 Jan 1997 05:04:29 GMT  
 parameter redefinition
|> Hello,
|>
[example code deleted]
|>
|> If there is an external RESET to the circuit, then I do not need
|> the initial statement. However, it is possible that there will
|> be no external RESET and I need to start with a particular value
|> (0 or 1) in the registers A,B,C,D.
|>
|> My first question is : how can I change my code such that the above
|> code can be synthesized ? (Assuming an initial statement is not
|> supported by the Verilog synthesizer..)
|> Can this be done without an external RESET
|> input to a module which would contain code as above?
|>
Cadence's synthesis tool, Synergy, supports the initial statement.
However, its mostly for modeling convenience and simulation efficiency
than anything else. We call it "power-on" reset.

Suppose you had a design that you expected to hit reset only once, at
power-on initialization. Why should you bother writing code that
checks reset every clock cycle. All you have to do declare a top level
pin as your reset, and Synergy connects the pin to either set or clear
of all your flops, depending on what was specified in the initial
block.

When comparing pre- and post-synthesis simulations, you have to allow
for the extra time needed to assert the reset pin. Also, if you DO
assert reset more than once, the pre-synthesis model will not respond.

If you do not have have an external pin, you can use a less than
orthodox method of an internally created power-on reset. This involves
tying reset to an RC network.

|> Secondly, approx. how many of the Verilog Synthesis Tools can handle
|> pullup and pulldown sources?
|>

"Handle" is a nebulous term. Pullup/down's on an otherwise undriven
wire are treated as 1/0's. If you have a pullup/down cell in your
target library, Synergy will map to them directly, but that's about
it. Logic optimization today only deals with 1's and 0's (with some X
and Z states thrown in)

Hope this helps

--
___________________________________________________________

Cadence Design, 270 Billerica Rd., Chelmsford MA 01824-4140
"I used to have Time. Now I have Twins"
___________________________________________________________



Sat, 11 Jan 1997 03:24:03 GMT  
 
 [ 10 post ] 

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