scope question 
Author Message
 scope question

I am reading a book about verilog that doesn't say a word about scope of
the variables. Am I to assume the same kind of rules as in C etc.?  Like
the variables inside a module have the module scope (i.e. accessible only
from within the module)? How about variables defined within a begin..end
block, block scope? I don't have a compiler set up to experiment...

Thanks,

Pavel



Fri, 08 Feb 2002 03:00:00 GMT  
 scope question
In Verilog you can reference a variable described anywhere
by specifying its full scope, e.g.:

top.block1.block2.a

So it is a bit different than C.

Variables defined in a module are accessible within a
task (or function) defined in that module.  I'm surprised
that nothing is mentioned about scope.

See the FAQ for a pointer to some free Verilog simulators.

/Ed

Quote:

> I am reading a book about verilog that doesn't say a word about scope of
> the variables. Am I to assume the same kind of rules as in C etc.?  Like
> the variables inside a module have the module scope (i.e. accessible only
> from within the module)? How about variables defined within a begin..end
> block, block scope? I don't have a compiler set up to experiment...

> Thanks,

> Pavel

--



Fri, 08 Feb 2002 03:00:00 GMT  
 scope question
Quote:

>In Verilog you can reference a variable described anywhere
>by specifying its full scope, e.g.:

>task (or function) defined in that module.  I'm surprised
>that nothing is mentioned about scope.

 I guess that's because Verilog is not a strict programming language,
 but a modelling language. You are modelling a hardware, and nothing
 stops you from placing a jumper from one end of a component to other
 place.
 Am i close (-;

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    webto:members.tripod.com/~vardhan ) "A variable" )



Sat, 09 Feb 2002 03:00:00 GMT  
 scope question

Quote:

> >In Verilog you can reference a variable described anywhere
> >by specifying its full scope, e.g.:

> >task (or function) defined in that module.  I'm surprised
> >that nothing is mentioned about scope.
>  I guess that's because Verilog is not a strict programming language,
>  but a modelling language. You are modelling a hardware, and nothing
>  stops you from placing a jumper from one end of a component to other
>  place.
>  Am i close (-;

In procedural programming languages like C or Pascal variables born and
die as the function that defines them is entered or exited. The objects
that are existing at any given moment depend on the run-time history of
the program and can not be predicted at compile time.
Some languages (e.g. Pascal) allow you to access variables in other
functions iff the compiler can prove that when your function is active
(and you reference the variable in an other function), the other function
is on its list of callers.

A Verilog program describes a *static* architecture of objects that
has a hierarchical definition relationship to each other.
It is therefore meaningful to reference any object from any place.

Well, I think :-)

Regards,

Zoltan

--
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
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Sun, 10 Feb 2002 03:00:00 GMT  
 scope question

Quote:
> A Verilog program describes a *static* architecture of objects that
> has a hierarchical definition relationship to each other.
> It is therefore meaningful to reference any object from any place.

Does this also apply to objects defined within functions
and tasks also? If this is the case, does recursion work in Verilog?
For recursion, all local variables have to be saved explicitly
by the compiler and later restored...whereas in most other language
implementations, when a function/procedure call is made, the storage
is allocated on the stack (which keeps extending for each new nested
call) and the stack shrinks as each function/procedure returns.

Thanx
Haneef



Tue, 12 Feb 2002 03:00:00 GMT  
 scope question

Quote:
> Does this also apply to objects defined within functions
> and tasks also? If this is the case, does recursion work in Verilog?
> For recursion, all local variables have to be saved explicitly
> by the compiler and later restored...whereas in most other language
> implementations, when a function/procedure call is made, the storage
> is allocated on the stack (which keeps extending for each new nested
> call) and the stack shrinks as each function/procedure returns.

Task variables are static. Although Verilog lets you recurively call a
task or call it in a re-entrant fashion, all variables will be shared
by all activation contexts. Only the flow of control will be maintained.

In C terms, a task is a function of which *all* local variables are
declared static and which (unlike a real C function) the input parameters
are static too.

The same is true for functions - even their input parameters have only
one instance. Best shown by a simple example:

module whatever;
integer d;

    always begin
        d = foo( 1 );
        $finish;        
    end

    function foo;
    input r;

      begin: name
      reg x;

        $display( "Before recursive call r=", r );
        if ( r == 1 ) x = whatever.foo( 0 );
        $display( "After recursive call r=", r );
        foo = r;
        end
    endfunction        
endmodule

Simulating it results:

Starting at time 0s. Sun Aug 29 10:20:26 1999
Simulating until no event ...
Before recursive call r=1
Before recursive call r=0
After recursive call r=0
After recursive call r=0
$finish called from file proba.v, line 6, in scope whatever, at time 0s

Regards,

Zoltan

--
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+



Thu, 14 Feb 2002 03:00:00 GMT  
 scope question

Quote:

> >In Verilog you can reference a variable described anywhere
> >by specifying its full scope, e.g.:

> >task (or function) defined in that module.  I'm surprised
> >that nothing is mentioned about scope.

>  I guess that's because Verilog is not a strict programming language,
>  but a modelling language. You are modelling a hardware, and nothing
>  stops you from placing a jumper from one end of a component to other
>  place.
>  Am i close (-;

        1) Verilog is a strict programming language, designed for
           modelling hardware.

        2) Verilog's heirarchical references are much like
           fortran's named commons.  If a routine knows the path
           to a variable in Verilog, it can read, write, and be
           sensitive to changes in that variable. Also, in FORTRAN
           if a subroutine knows the name of a common region, it can
           read and write any variable declared in that common.

        3) There is strict definitions of scope; see Section 12.4 of
           the IEEE 1364 Standard Hardware Description Language based
           on the Verilog Hardware Description Language,
           ISBN1-55937-727-5. Also the rules of name spaces are
           defined in Section 3.11. Finally, also note that the PLI
           has access to every variable in the design, and hence is
           another participant in any scopeing issues.

        4) In Verilog-1999 we have approved a re-entrant task and
           function declarations. As is noted in other postings, today
           verilog tasks and functions are not re-entrant; instead
           there is just one copy of any variable per instance of a
           module.

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  /\///\   <http://www.surefirev.com>   408-374-4174 FAX
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Fri, 15 Feb 2002 03:00:00 GMT  
 scope question
Is there a spec for Verilog 99 publically available yet? Also will it
support multidimensional arrays and structures?

Josh

Quote:



> > >In Verilog you can reference a variable described anywhere
> > >by specifying its full scope, e.g.:

> > >task (or function) defined in that module.  I'm surprised
> > >that nothing is mentioned about scope.

> >  I guess that's because Verilog is not a strict programming language,
> >  but a modelling language. You are modelling a hardware, and nothing
> >  stops you from placing a jumper from one end of a component to other
> >  place.
> >  Am i close (-;

>         1) Verilog is a strict programming language, designed for
>            modelling hardware.

>         2) Verilog's heirarchical references are much like
>            FORTRAN's named commons.  If a routine knows the path
>            to a variable in Verilog, it can read, write, and be
>            sensitive to changes in that variable. Also, in FORTRAN
>            if a subroutine knows the name of a common region, it can
>            read and write any variable declared in that common.

>         3) There is strict definitions of scope; see Section 12.4 of
>            the IEEE 1364 Standard Hardware Description Language based
>            on the Verilog Hardware Description Language,
>            ISBN1-55937-727-5. Also the rules of name spaces are
>            defined in Section 3.11. Finally, also note that the PLI
>            has access to every variable in the design, and hence is
>            another participant in any scopeing issues.

>         4) In Verilog-1999 we have approved a re-entrant task and
>            function declarations. As is noted in other postings, today
>            verilog tasks and functions are not re-entrant; instead
>            there is just one copy of any variable per instance of a
>            module.

> --

>    /\//    SureFire Verification Inc.   408-374-4100 x 100
>   /\///\   <http://www.surefirev.com>   408-374-4174 FAX
>  _\///\/        Formerly Silicon Sorcery
>   \//\/    Get my verilog emacs mode from
>     \/     <http://www.surefirev.com/verilog-mode.html>



Sat, 16 Feb 2002 03:00:00 GMT  
 scope question


Quote:
> Is there a spec for Verilog 99 publically available yet?

        It is publically available if you join the committee; we
        welcome new members!  It is due to go to ballet later this
        year; we are looking over the penultimate draft right now.

Quote:
> Also will it support multidimensional arrays and structures?

        At present the answer is Yes to multi dimensional arrays, and
        No to structures.

Quote:

> Josh

--

   /\//    SureFire Verification Inc.   408-374-4100 x 100
  /\///\   <http://www.surefirev.com>   408-374-4174 FAX
 _\///\/        Formerly Silicon Sorcery
  \//\/    Get my verilog emacs mode from
    \/     <http://www.surefirev.com/verilog-mode.html>


Sat, 16 Feb 2002 03:00:00 GMT  
 scope question
There is no recursion in verilog.  Data in task, functions, and named
blocks have unique scopes.  however data in tasks and functions are
static, and there is only a single copy per module instance, so a
reentrant task or function will overwrite its only copy of the data.

Quote:

> > A Verilog program describes a *static* architecture of objects that
> > has a hierarchical definition relationship to each other.
> > It is therefore meaningful to reference any object from any place.

> Does this also apply to objects defined within functions
> and tasks also? If this is the case, does recursion work in Verilog?
> For recursion, all local variables have to be saved explicitly
> by the compiler and later restored...whereas in most other language
> implementations, when a function/procedure call is made, the storage
> is allocated on the stack (which keeps extending for each new nested
> call) and the stack shrinks as each function/procedure returns.

> Thanx
> Haneef

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Wed, 06 Mar 2002 03:00:00 GMT  
 
 [ 12 post ] 

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