ncverilog and mixed vhdl-verilog simulation 
Author Message
 ncverilog and mixed vhdl-verilog simulation

Hi,

I have to use ncsim in order to run a mixed vhdl and verilog
simulation:
I have a verilog netlist, in which a module is instanciated.
This module is just instanciated with its connections, but not
decribed neither declared in verilog.
The description is in a VHDL file (entity and rtl code).
The bench is in vhdl.

I know vhdl, but not verilog.

I tried to use ncvdhl, and then ncverilog with the +mixedlang option,
but it doesn't work (the component is unbound).

Could you please tell me:
- How to instanciate a VHDL module in a verilog netlist (especially
the declaration part) ?
- How to configure the libraries (in which library should I compile
the vhdl part, and the verilog netlist) ?
- Is there any problems with the busses naming convention between
verilog and vhdl?

The command I used are:
* ncvhdl +work <vhdl_lib> PROGRAM_ENTITY.vhd
* ncvdhl +work <vhdl_lib> PROGRAM_RTL.vhd
* ncverilog +mixedlang .... -v <libraries> <verilog netlist> (other
options I don't remember, but not very important for my trouble)

Then a makefile compiles and elaborates the bench.

The verilog command echoes that my vhdl component is not bound, which
makes me very sad!!

Thank you for your help

Jerome.



Mon, 10 Nov 2003 22:03:38 GMT  
 ncverilog and mixed vhdl-verilog simulation
<crossposted to comp.lang.vhdl>

 > Hi,
 >
 > I have to use ncsim in order to run a mixed vhdl and verilog
 > simulation:
 > I have a verilog netlist, in which a module is instanciated.
 > This module is just instanciated with its connections, but not
 > decribed neither declared in verilog.
 > The description is in a VHDL file (entity and rtl code).
 > The bench is in vhdl.

Let me get this straight:

Bench (VHDL top) - "vhdl_bench" (architecture "top")
||
Verilog netlist - "vlog_netlist"
||
VHDL entity and architecture - vhdl_module (architecture "rtl")

 > I know vhdl, but not verilog.
 >
 > I tried to use ncvdhl, and then ncverilog with the +mixedlang option,
 > but it doesn't work (the component is unbound).

You need to create a VHDL to Verilog shell (ncshell) to
instantiate the VHDL module in Verilog. Then you need
to create a Verilog to VHDL shell to instantiate the
Verilog netlist in your VHDL testbench. You also need
to be careful with VHDL generics (some can't be translated).

 > Could you please tell me:
 > - How to instanciate a VHDL module in a verilog netlist (especially
 > the declaration part) ?
 > - How to configure the libraries (in which library should I compile
 > the vhdl part, and the verilog netlist) ?

You have to choose whether or not you want to keep
separate compiled libraries for blocks, groups, etc.
You could conceivably do everything in one library.

I would suggest the following, using the names I picked
above. I assume that your VHDL files contain only one
module each with both the entity and architecture. I'll
also assume that you're using only one library called
"lib0". You might also want to check your options. There's
one where the case of the module names is preserved, and
another where the the case is changed to all uppercase.

1> ncvhdl vhdl_module.vhd
2> ncshell -messages -import vhdl -into verilog lib0.vhdl_module:rtl
This creates a Verilog shell file called "vhdl_module.vs". You need
to specify the architecture ("rtl" here) name after the entity name.
3> ncvlog vhdl_module.vs
4> ncvlog vlog_netlist.v
5> ncshell -messages -import verilog -into vhdl -generic
lib0.verilog_netlist:module
This creates a VHDL entity shell file called vlog_netlist.vhd
6> ncvhdl vlog_netlist.vhd
7> ncvhdl vhdl_bench.vhd
8> ncelab -messages lib0.vhdl_bench:top
9> ncsim -gui lib0.vhdl_bench:top &

 > - Is there any problems with the busses naming convention between
 > verilog and vhdl?

Sometimes - you have to just try things out and see if they work.

I would suggest looking at the OpenWin help on ncshell. There
should be a section on mixed Verilog and VHDL simulations in
the ncsim user's guide.

 > The command I used are:
 > * ncvhdl +work <vhdl_lib> PROGRAM_ENTITY.vhd
 > * ncvdhl +work <vhdl_lib> PROGRAM_RTL.vhd
 > * ncverilog +mixedlang .... -v <libraries> <verilog netlist> (other
 > options I don't remember, but not very important for my trouble)
 >
 > Then a makefile compiles and elaborates the bench.
 >
 > The verilog command echoes that my vhdl component is not bound, which
 > makes me very sad!!
 >
 > Thank you for your help
 >
 > Jerome.

If you have any problems, feel free to post a follow-up or email me.
It took me a while to figure out how things work in NC-Affirma, but
it's a lot easier if you can get someone to see you through.

Yu-Ping Wang
Berkeley, California



Tue, 11 Nov 2003 01:59:22 GMT  
 
 [ 2 post ] 

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