TO UK HDL USERS: Verilog events at Silicon Design, Oct 25-26 
Author Message
 TO UK HDL USERS: Verilog events at Silicon Design, Oct 25-26

To:     HDL Users based in the UK

Announcing:     Verilog activities at the Silicon Design Show

Venue:          Heathrow, UK
                ------------
Date:           October 25-26

A series of Verilog activities have been organised for the Silicon Design
show at the Heathrow Ramada Hotel in the UK  _next_week_.

The aim is to provide the latest information on Verilog and measure the need
for communications amongst users and potential users of Verilog in the UK.

All HDL users should find some items of interest:
*************
        Tuesday 25th
                10-12:30 TUTORIAL: Verilog, the language & its applications

                10:00   Introduction to the Language
                        <FOR NEW VERILOG USERS & VHDL USERS>
                11:00   Coffee break
                11:30   Verilog for Real Designs - Using with VHDL & why
                        <FOR NEW & ESTABLISHED VERILOG USERS & VHDL USERS>
                12:00   Panel Q&A: Strengths & applications of Verilog
                        with Vendors and experienced Users
                        <FOR NEW & ESTABLISHED VERILOG USERS & VHDL USERS>

                12:30   Buffet Lunch

                13:00   Verilog Users kick off meeting
                        <EVERYONE WITH A POTENTIAL INTEREST IN VERILOG>
                14:00   Ends

        Wednesday 26th
                10-12:30 TUTORIAL: VHDL or Verilog?
                        <FOR NEW & ESTABLISHED VERILOG USERS & VHDL USERS>
                10:00   First half
                11:00   Coffee break
                11:30   Second half!

                12:30   Buffet Lunch

                13:00   Verilog Users kick off meeting
                        <EVERYONE WITH A POTENTIAL INTEREST IN VERILOG>
                14:00   Ends

Tutorials cost 50 GBP + VAT for the 2 hour session
                (contact EDA Limited on 071-404-0564)

Attendance at the Verilog Users kick off meeting is free.

All activities are in Conference Room B (the Windsor Room - no royalty in
attendance! :)...

Thanks for the bandwidth
        (especially to non UK users if this escapes from the UK)

Jon
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------------------<Design & Methodology Solutions>----------------------------

===========================================================================
Tuesday 25th October 1994

Tutorial                                        Organisers: NEuW

                Verilog HDL - the language and its applications

        10:00am An Introduction to Verilog
                        Peter Flake, Elda Technology Ltd

                Discussing the main features of Verilog and how they are used
                in simulation and synthesis.

                        Verilog will be considered in four parts:

                                'Core' hardware description language

                                ASIC library constructs

                                Input, output and control constructs

                                Programming language interface

                        Finally Verilog and VHDL will be compared

        11:00am Coffee break

        11:30am Using Verilog for Real designs
                        John Goodenough, Sheffield Silicon Systems Group

                Discusses the use of a mixed Verilog and VHDL methodology
                in the successful design of a 1.5 million transistor Video
                Signal Processing chip. Based on John's award winning paper
                at the VHDL User Group this talk has been refocussed to
                discuss the reasons for using and applicability of Verilog.

                        This will cover:
                                - modelling
                                - synthesis
                          and   - verification

                This presentation will set the scene for:

        12:00   Strengths and applications of Verilog
                        - a panel session answering your questions.

                        THE USERS
                        Peter Flake     Elda Technology Ltd
                        Ian Gibbins     NEuW ASIC Methodology Consultant
                        John Goodenough Sheffield Silicon Systems Group
                        THE VENDORS
                        Simon Davidmann Chronologic Simulation
                        Jeff Edson      Intergraph
                        tba             Cadence Design Systems                        
                  Moderator
                        Jon Howes       NEuW Limited

                The panelists will give a short statement of their view
                of the strengths and applications of Verilog.

                The focus of this session will be on answering questions from
                the audience.

        12:30pm Tutorial ends

                Open invitation to join the Verilog User meeting at 13:00

        Each attendee will be supplied with a copy of the course materials.

===========================================================================
Wednesday 26th October

Tutorial                                        Organisers: Doulos
        10:00          
                VHDL or Verilog?

                        VHDL and Verilog Head to Head

                An Independent Technical and Commercial Comparison

                Presented by Mike Smith, Doulos

                This 2 hour tutorial will provide guidance for organisations
                faced with an HDL choice, by tackling issues such as:

                - What are the similarities/differences between
                   VHDL & Verilog?

                - Should my company move from Verilog to VHDL?

                - Can my company afford to support both VHDL and Verilog?

                - Will Verilog die?

                - How vital is VITAL?

        12:30   Tutorial ends

                Open invitation to join the Verilog User meeting at 13:00  

        Each attendee will be supplied with a copy of the course materials.

===========================================================================

SILICON DESIGN SHOW, UK, OCT 25-26

VERILOG USERS IN THE UK - Kick Off Meeting

Come along to Conference room B 1pm-2pm on either day of the Silicon Design
Show and find out more and exchange ideas about Verilog HDL. There will be a
brief update on Verilog and potential and existing users will be encouraged
to discuss the needs for some form of Verilog UK interest group - to provide
a communication medium to keep users informed on Verilog and related tools
and methods. This short lunchtime session will include:

        Buffet Lunch from 12:30

        An update on Open Verilog International (OVI) activities

                        Simon Davidmann, European OVI coordinator        
                                         & Chronologic Simulation

        IEEE 1364 status report on progress with Verilog HDL becoming
                the new IEEE HDL standard

                        Jon Howes, NEuW Limited

        Open discussion on users needs and requirements
                for a Verilog User Group or communications forum.

                        - with input from key Verilog experts

----

The idea of these shortish (1hr) lunchtime sessions during the
conference/exhibition is to get designers/users together who are interested
in sharing information related to the use of the Verilog HDL and associated
methodologies.

The use of HDLs is growing in FPGA/ASIC/IC/Systems design and many new users
are adopting the associated methods of HDL design and synthesis. The users
of Verilog can now purchase their Verilog simulators from several sources
(including PC based tools) and need access to the latest information to
make decisions on their future design and EDA strategy.

The Verilog HDL is in widespread use throughout the world and many
users and new users want a forum for learning more, and hearing what is
happening in terms of usage and product developments.

A communication medium seems to be needed to provide designers with access to
new information.

It is the objective of these lunch time sessions to measure user interest
and help form plans for such a Verilog communications forum.



Tue, 08 Apr 1997 04:24:29 GMT  
 
 [ 1 post ] 

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