spice netlist --> verilog conversion tool 
Author Message
 spice netlist --> verilog conversion tool

Hi,

I'm looking for a tool that can convert [h]spice netlists to
verilog structure model.  Of course, netlists contain only 'macros',
no transistors or capacitors.

If anybody know of such a tool, please give me a pointer to it.

Thanks,
Eiki Ito



Sat, 17 Apr 1999 03:00:00 GMT  
 
 [ 1 post ] 

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