Microcontroller ASIC Design Engineers - Western Digital - Irvine, CA 
Author Message
 Microcontroller ASIC Design Engineers - Western Digital - Irvine, CA

The I/O Products Division of Western Digital Corporation is dedicated
to the design of world-class high performance semiconductor products.
We stand by our commitment to innovation and customer satisfaction.
Join us in the following opportunity in the Fibre Channel Design
organization at our IRVINE, CALIFORNIA facility.

SENIOR DESIGN ENGINEER

Design engineer to work on 100K gate CMOS microcontrollers.  
Experience (3 years) using logic simulators, timing simulators, design
verification tools and workstations is required.  Logic design
experience on Standard Cell CMOS VLSI is required.

The following specific tool knowledge/experience is desirable (in
order of priority):  Verilog HDL programming; Synopsys logic/test
synthesis; Zycad hardware acceleration; VHDL programming; Veritime
static timing analysis; SES Workbench architectural simulation; and
Sunrise ATPG.

The following specific application knowledge/experience is desirable
(in order of priority):  Fibre Channel standards and implementation;
SCSI standards and implementation; SSA standards and implementation;
host bus adaptor implementation; and disk drive I/O controller
implementation.

We offer competitive compensation and a flexible/comprehensive
benefits package.  Principals only need apply. EOE

For immediate consideration please mail or fax your resume to:

     Western Digital Corporation
     ATTN: Hal Kraft, MS 712-D
     8105 Irvine Center Drive
     Irvine, CA  92718

     FAX 714.932.6496



Sun, 13 Apr 1997 05:14:03 GMT  
 Microcontroller ASIC Design Engineers - Western Digital - Irvine, CA
The I/O Products Division of Western Digital Corporation is dedicated
to the design of world-class high performance semiconductor products.
We stand by our commitment to innovation and customer satisfaction.
Join us in the following opportunity in the Fibre Channel Design
organization at our IRVINE, CALIFORNIA facility.

SENIOR DESIGN ENGINEER

Design engineer to work on 100K gate CMOS microcontrollers.  
Experience (3 years) using logic simulators, timing simulators, design
verification tools and workstations is required.  Logic design
experience on Standard Cell CMOS VLSI is required.

The following specific tool knowledge/experience is desirable (in
order of priority):  Verilog HDL programming; Synopsys logic/test
synthesis; Zycad hardware acceleration; VHDL programming; Veritime
static timing analysis; SES Workbench architectural simulation; and
Sunrise ATPG.

The following specific application knowledge/experience is desirable
(in order of priority):  Fibre Channel standards and implementation;
SCSI standards and implementation; SSA standards and implementation;
host bus adaptor implementation; and disk drive I/O controller
implementation.

We offer competitive compensation and a flexible/comprehensive
benefits package.  Principals only need apply. EOE

For immediate consideration please mail or fax your resume to:

     Western Digital Corporation
     ATTN: Hal Kraft, MS 712-D
     8105 Irvine Center Drive
     Irvine, CA  92718

     FAX 714.932.6496



Sat, 19 Apr 1997 01:56:22 GMT  
 
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