generate statement 
Author Message
 generate statement

Hi,
I'am quite  new to verilog. I used the "generate " statement in  a for
loop in VHDL to create multiple instances of a given component. Is there
a way to do thing similarly in VERILOG?
Thanks for any hint.
Guy


Tue, 11 Jan 2005 13:29:50 GMT  
 generate statement

Quote:

> Hi,
> I'am quite  new to verilog. I used the "generate " statement in  a for
> loop in VHDL to create multiple instances of a given component. Is there
> a way to do thing similarly in VERILOG?
> Thanks for any hint.
> Guy

I have seen that a similar question was already posted in this group and
that  array instances should do the job although it is not really supported
by all systems.
But the thing that I don't realy get is that  I can use the loop index of a
for loop to control the port binding wihtin a generate assignment in VHDL.
whereas this wont be the case in VERILOG since the "for" loop is purely
procedural.
Guy


Tue, 11 Jan 2005 14:16:58 GMT  
 generate statement
Hello/

Quote:
> Hi,
> I'am quite  new to verilog. I used the "generate " statement in  a for
> loop in VHDL to create multiple instances of a given component. Is there
> a way to do thing similarly in VERILOG?

unfortunately, there is no "generate" in Verilog.
An obviously missing feature in Verilog, compared to VHDL
/Abhijit


Tue, 11 Jan 2005 16:51:47 GMT  
 generate statement
Hi,
  verilog 2000 supports generate and in fact a host of other vhdl style
features - notably configurations. but i doubt whether any tool has full
support for all of these.
Quote:


> > Hi,
> > I'am quite  new to verilog. I used the "generate " statement in  a for
> > loop in VHDL to create multiple instances of a given component. Is there
> > a way to do thing similarly in VERILOG?
> > Thanks for any hint.
> > Guy

> I have seen that a similar question was already posted in this group and
> that  array instances should do the job although it is not really supported
> by all systems.
> But the thing that I don't realy get is that  I can use the loop index of a
> for loop to control the port binding wihtin a generate assignment in VHDL.
> whereas this wont be the case in VERILOG since the "for" loop is purely
> procedural.
> Guy



Tue, 11 Jan 2005 18:04:30 GMT  
 generate statement
Hi,

You need to use System Verilog (I cannot remember if Verilog 2001 has this).
Of course, you will need a Verilog simulator that support it.

Regards,
Eng Han
www.eda-utilities.com

Quote:

> Hi,
> I'am quite  new to verilog. I used the "generate " statement in  a for
> loop in VHDL to create multiple instances of a given component. Is there
> a way to do thing similarly in VERILOG?
> Thanks for any hint.
> Guy



Wed, 12 Jan 2005 23:54:35 GMT  
 generate statement

Quote:

> Hi,

> You need to use System Verilog (I cannot remember if Verilog 2001 has
> this). Of course, you will need a Verilog simulator that support it.

How about synthesis support is that available?

Cheers

Stefan

--
Stefan Doll, Mnchen, Germany
http://www.stefanVHDL.com



Thu, 13 Jan 2005 00:50:34 GMT  
 generate statement
Hi Stefan,

I believe Get2Chip synthesis software support generate statement in
Verilog. Anyone disagree?

Regards,
Eng Han
www.eda-utilities.com

Quote:


> > Hi,

> > You need to use System Verilog (I cannot remember if Verilog 2001 has
> > this). Of course, you will need a Verilog simulator that support it.

> How about synthesis support is that available?

> Cheers

> Stefan

> --
> Stefan Doll, Mnchen, Germany
> http://www.stefanVHDL.com



Sat, 15 Jan 2005 23:36:08 GMT  
 
 [ 7 post ] 

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