Compiling Altera LPM on leonardo 
Author Message
 Compiling Altera LPM on leonardo

Hi,

I generated a verilog module of lpm_ram_dp using Quartus
megafunction wizard.

module dpmem (
      data,
      wraddress,
      rdaddress,
      wren,
      rden,
      wrclock,
      rdclock,
      q);

      input      [31:0]  data;
      input      [4:0]  wraddress;
      input      [4:0]  rdaddress;
      input        wren;
      input        rden;
      input        wrclock;
      input        rdclock;
      output      [31:0]  q;

      wire [31:0] sub_wire0;
      wire [31:0] q = sub_wire0[31:0];

      lpm_ram_dp      lpm_ram_dp_component (
                        .rdclock (rdclock),
                        .wren (wren),
                        .wrclock (wrclock),
                        .rden (rden),
                        .data (data),
                        .rdaddress (rdaddress),
                        .wraddress (wraddress),
                        .q (sub_wire0));
      defparam
            lpm_ram_dp_component.lpm_width = 32,
            lpm_ram_dp_component.lpm_widthad = 5,
            lpm_ram_dp_component.lpm_indata = "REGISTERED",
            lpm_ram_dp_component.lpm_wraddress_control
= "REGISTERED",
            lpm_ram_dp_component.lpm_rdaddress_control
= "REGISTERED",
            lpm_ram_dp_component.lpm_outdata = "REGISTERED",
            lpm_ram_dp_component.lpm_hint = "USE_EAB=ON";

endmodule

I am trying to synthesize it using altera Leonardo spectrum but I
get error message indicating that this module is not a defined
module or gate in a library knowing that I loaded Apex library from
Leonardo.

This problem occured also when I try to make a instance of this
module in my design which is the most important for me.

I tried it using VHDL and it went OK but I had to change the
instance name in the resulted EDF file to compile it in Quartus.

do you have any suggestion to this problem?


Thanks in advance
Jamil Khatib



Thu, 09 Jun 2005 18:43:41 GMT  
 Compiling Altera LPM on leonardo
Try to compile again with these 2 lines added to your defparam...

 lpm_ram_dp_component.use_eab = "ON",
 lpm_ram_dp_component.lpm_type = "LPM_RAM_DP";
 lpm_ram_dp_component.rden_used = "TRUE",
 lpm_ram_dp_component.intended_device_family = "UNUSED",

And remove this line:

Quote:
>             lpm_ram_dp_component.lpm_hint = "USE_EAB=ON";

____________
Brian Guralnick

Quote:

> Hi,

> I generated a verilog module of lpm_ram_dp using Quartus
> megafunction wizard.

> module dpmem (
>       data,
>       wraddress,
>       rdaddress,
>       wren,
>       rden,
>       wrclock,
>       rdclock,
>       q);

>       input      [31:0]  data;
>       input      [4:0]  wraddress;
>       input      [4:0]  rdaddress;
>       input        wren;
>       input        rden;
>       input        wrclock;
>       input        rdclock;
>       output      [31:0]  q;

>       wire [31:0] sub_wire0;
>       wire [31:0] q = sub_wire0[31:0];

>       lpm_ram_dp      lpm_ram_dp_component (
>                         .rdclock (rdclock),
>                         .wren (wren),
>                         .wrclock (wrclock),
>                         .rden (rden),
>                         .data (data),
>                         .rdaddress (rdaddress),
>                         .wraddress (wraddress),
>                         .q (sub_wire0));
>       defparam
>             lpm_ram_dp_component.lpm_width = 32,
>             lpm_ram_dp_component.lpm_widthad = 5,
>             lpm_ram_dp_component.lpm_indata = "REGISTERED",
>             lpm_ram_dp_component.lpm_wraddress_control
> = "REGISTERED",
>             lpm_ram_dp_component.lpm_rdaddress_control
> = "REGISTERED",
>             lpm_ram_dp_component.lpm_outdata = "REGISTERED",
>             lpm_ram_dp_component.lpm_hint = "USE_EAB=ON";

> endmodule

> I am trying to synthesize it using altera Leonardo spectrum but I
> get error message indicating that this module is not a defined
> module or gate in a library knowing that I loaded Apex library from
> Leonardo.

> This problem occured also when I try to make a instance of this
> module in my design which is the most important for me.

> I tried it using VHDL and it went OK but I had to change the
> instance name in the resulted EDF file to compile it in Quartus.

> do you have any suggestion to this problem?


> Thanks in advance
> Jamil Khatib



Fri, 10 Jun 2005 10:15:25 GMT  
 Compiling Altera LPM on leonardo
Jamil,
   You should blackbox the instance of the memory generated using the
Megawizard before synthesizing with Leonardo. This is described in detail in
the Quartus II online help. Open the Online Help and search for "Black box".
This will identify several articles. Select the one with the title "Creating
& Instantiating a Verilog HDL Function for Use with the LeonardoSpectrum
Software". This discusses the steps needed to blackbox a Megawizard
generated function properly. Hope this helps.

- Subroto Datta


Quote:
> Hi,

> I generated a verilog module of lpm_ram_dp using Quartus
> megafunction wizard.

> module dpmem (
>       data,
>       wraddress,
>       rdaddress,
>       wren,
>       rden,
>       wrclock,
>       rdclock,
>       q);

>       input      [31:0]  data;
>       input      [4:0]  wraddress;
>       input      [4:0]  rdaddress;
>       input        wren;
>       input        rden;
>       input        wrclock;
>       input        rdclock;
>       output      [31:0]  q;

>       wire [31:0] sub_wire0;
>       wire [31:0] q = sub_wire0[31:0];

>       lpm_ram_dp      lpm_ram_dp_component (
>                         .rdclock (rdclock),
>                         .wren (wren),
>                         .wrclock (wrclock),
>                         .rden (rden),
>                         .data (data),
>                         .rdaddress (rdaddress),
>                         .wraddress (wraddress),
>                         .q (sub_wire0));
>       defparam
>             lpm_ram_dp_component.lpm_width = 32,
>             lpm_ram_dp_component.lpm_widthad = 5,
>             lpm_ram_dp_component.lpm_indata = "REGISTERED",
>             lpm_ram_dp_component.lpm_wraddress_control
> = "REGISTERED",
>             lpm_ram_dp_component.lpm_rdaddress_control
> = "REGISTERED",
>             lpm_ram_dp_component.lpm_outdata = "REGISTERED",
>             lpm_ram_dp_component.lpm_hint = "USE_EAB=ON";

> endmodule

> I am trying to synthesize it using altera Leonardo spectrum but I
> get error message indicating that this module is not a defined
> module or gate in a library knowing that I loaded Apex library from
> Leonardo.

> This problem occured also when I try to make a instance of this
> module in my design which is the most important for me.

> I tried it using VHDL and it went OK but I had to change the
> instance name in the resulted EDF file to compile it in Quartus.

> do you have any suggestion to this problem?


> Thanks in advance
> Jamil Khatib



Fri, 10 Jun 2005 11:31:53 GMT  
 
 [ 3 post ] 

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