Verilog wire initialization 
Author Message
 Verilog wire initialization

Hi,

When I try to simulate the following verilog model, the net 'out'
goes to unknown whenever both the inputs are '1'.  My intention is to
initialize the 'out' to 0 and then to propagate the 'and' of the
inputs to the output.  Is there any way I can do this?.  I tried
with 'initial' construct but it did not work either.
Thanks in advance

P.S. A vhdl equivalent of this model works as I wanted.

---------------------------------------------------------------

module test( in1, in2) ;

input in1, in2 ;

wire out = 0 ;

assign out = in1 & in2 ;

endmodule

---------------------------------------------------------------

Naveen

--



Sat, 06 Dec 1997 03:00:00 GMT  
 Verilog wire initialization
Naveen,

the code that you have:

Quote:
>module test( in1, in2) ;

>input in1, in2 ;

>wire out = 0 ;

>assign out = in1 & in2 ;

>endmodule

doesn't work because a wire initialization in Verilog acts as a concurrent assignment.
Therefore, when you have in1 and in2 both 1, out is driven by both 0 and 1, which
results
in X. Your version with 'initial' (I assume) doesn't work because, for initial, you have
to have 'out' declared as a reg, and you have it as a wire. If out is a reg, you cannot
use a concurrent assignment anymore.

The following will do what you want:

module test (in1, in2);
input in1, in2;
reg out;

         out = in1 & in2;
initial out = 0;
endmodule

The always clause in this case acts as your concurrent assignment.

        *********************************************************
        *  Sergei Sokolov          Alternative System Concepts  *
        *  22 Haverhill Rd., P.O. Box 128    Windham, NH 03087  *
        *  phone: 603-437-2234               fax: 603-437-2722  *

        *                                                       *
        *********************************************************

P.S. The VHDL version with a default 'out' initialization worked because, in
VHDL, initializations are overwritten by any assignment.



Sun, 07 Dec 1997 03:00:00 GMT  
 Verilog wire initialization
when using initial blocks, you can only do register assignment.  There
is two ways I can think of right now.  One is to change 'out' to a
register, and have an initial and always blocks handle the logic.

--------------
reg     out;

initial
        out = 0;


        out = in1 & in2;
-------------
If you have to have a wire as the output, you may do the following.

--------------
reg     out_reg;
wire    out;

initial
        out_reg = 0;


        out_reg = in1 & in2;

assign  out = out_reg;
--------------

regards,

benedict ng

Quote:

>Hi,

>When I try to simulate the following verilog model, the net 'out'
>goes to unknown whenever both the inputs are '1'.  My intention is to
>initialize the 'out' to 0 and then to propagate the 'and' of the
>inputs to the output.  Is there any way I can do this?.  I tried
>with 'initial' construct but it did not work either.
>Thanks in advance

>P.S. A vhdl equivalent of this model works as I wanted.

>---------------------------------------------------------------

>module test( in1, in2) ;

>input in1, in2 ;

>wire out = 0 ;

>assign out = in1 & in2 ;

>endmodule

>---------------------------------------------------------------

>Naveen

>--




Fri, 12 Dec 1997 03:00:00 GMT  
 Verilog wire initialization
|> Naveen,
|>
|> the code that you have:
|>
|> >module test( in1, in2) ;
|> >
|> >input in1, in2 ;
|> >
|> >wire out = 0 ;
|> >
|> >assign out = in1 & in2 ;
|> >
|> >endmodule
|> >
|>
|> doesn't work because a wire initialization in Verilog acts as a concurrent assignment.
|> Therefore, when you have in1 and in2 both 1, out is driven by both 0 and 1, which
|> results
|> in X. Your version with 'initial' (I assume) doesn't work because, for initial, you have
|> to have 'out' declared as a reg, and you have it as a wire. If out is a reg, you cannot
|> use a concurrent assignment anymore.
|>
|> The following will do what you want:
|>
|> module test (in1, in2);
|> input in1, in2;
|> reg out;

|>    out = in1 & in2;
|> initial out = 0;
|> endmodule
|>
|> The always clause in this case acts as your concurrent assignment.
|>
|>   *********************************************************
|>   *  Sergei Sokolov          Alternative System Concepts  *
|>   *  22 Haverhill Rd., P.O. Box 128    Windham, NH 03087  *
|>   *  phone: 603-437-2234               fax: 603-437-2722  *

|>   *                                                       *
|>   *********************************************************
|>
|> P.S. The VHDL version with a default 'out' initialization worked because, in
|> VHDL, initializations are overwritten by any assignment.
|>

What Sergei says above is correct.  However, I want to add one small clarification
"just in case".

Naveen did not say that he planned to synthesize his model, BUT, if the intention
is to synthesize it, be
aware that the initial statement is a non-synthesizable construct.  The effect
of that is that a synthesis tool will ignore the construct.  That in and of
itself isn't a problem, but it does leave open the possibility that a simulation
of the design before synthesis will not match a corresponding simulation of the
synthesized design.

Another way to handle Naveen's problem might be to ensure that the inputs
in1 and in2 are themselves initialized.  That will have the effect of initializing
the wire out, and more closely resemble actual hardware to boot.

Again, this isn't a problem if the model isn't going to be synthesized, but is
a potential pitfall if it is...

--

                 Goes to show, you don't ever know...



Mon, 15 Dec 1997 03:00:00 GMT  
 
 [ 4 post ] 

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