Any verilog optimizers out there ?? 
Author Message
 Any verilog optimizers out there ??

Is there anything that will optimize the verilog
output that my tool is dumping. I heard about
some freeware called Espresso from Univ Berkeley,
but cannot get my hand on it.

Any recommendations ..

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Tue, 04 Mar 2003 03:00:00 GMT  
 Any verilog optimizers out there ??

Quote:

> Is there anything that will optimize the verilog
> output that my tool is dumping.

Icarus Verilog includes some basic optimizations (constant propogation,
dead gate elimination, constant conditions in conditionals, etc.) but
the
Verilog output backend is pretty rusty.

        <http://www.icarus.com/eda/verilog/>

--
Steve Williams                "The woods are lovely, dark and deep.


http://www.picturel.com       And lines to code before I sleep."



Thu, 06 Mar 2003 03:00:00 GMT  
 Any verilog optimizers out there ??
The DMS Reengineering Toolkit is generalized compiler technology
used to automate custom analysis/modifications to large scale
specifications.

DMS processes Verilog, and can be used to straightforwardly code
many interesting optimizations such as the ones listed below.
DMS also includes a prettyprinter, so the result output is clean and neat.

More details can be found at:
http://www.semdesigns.com/Products/DMS/DMSTookit.html.

--

Semantic Designs, Inc., www.semdesigns.com FAX 512-250-1191
12636 Research Blvd #C214, Austin, Texas 78759


Quote:

> > Is there anything that will optimize the verilog
> > output that my tool is dumping.

> Icarus Verilog includes some basic optimizations (constant propogation,
> dead gate elimination, constant conditions in conditionals, etc.) but
> the
> Verilog output backend is pretty rusty.

> <http://www.icarus.com/eda/verilog/>

> --
> Steve Williams                "The woods are lovely, dark and deep.


> http://www.picturel.com       And lines to code before I sleep."



Fri, 07 Mar 2003 03:00:00 GMT  
 
 [ 3 post ] 

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