VHDL generate statement conversion 
Author Message
 VHDL generate statement conversion

I'm new to Verilog and just learned that there is nothing
like the VHDL generate statement in Verilog. So my
question is how do you convert something like the following into
Verilog. I want to instantiate a component MOD_A inside the
xyz entity when the generic PAR_G is set to 0 or instantiate
the component MOD_B when the generic is set to 1 or instantiate
the component MOD_C when the generic is set to 2.

Thanks in advance !

...

library work;
use work.all;

...

entity xyz is
  generic (
              PAR_G  : integer    -- valid values are 0, 1 or 2
           );

  port     (
               ....
            );
end xyz;

architecture beh of xyz .....
    ...
begin

         if PAR_G = 0 generate
             u_calc : MOD_A
             port map (
                         A => ...
                         B => ...
                         C => ...
                       );
         end generate;

         if PAR_G = 1 generate
             u_calc : MOD_B
             port map (
                         A => ...
                         B => ...
                         C => ...
                         D => ...
                       );
         end generate;

         if PAR_G = 2 generate
             u_calc : MOD_C
             port map (
                         A => ...
                         B => ...
                         C => ...
                         D => ...
                         E => ...
                       );
         end generate;

end beh;



Wed, 30 Nov 2005 00:58:56 GMT  
 VHDL generate statement conversion

Quote:
> I'm new to Verilog and just learned that there is nothing
> like the VHDL generate statement in Verilog. So my
> question is how do you convert something like the following into
> Verilog. I want to instantiate a component MOD_A inside the
> xyz entity when the generic PAR_G is set to 0 or instantiate
> the component MOD_B when the generic is set to 1 or instantiate
> the component MOD_C when the generic is set to 2.

You are presenting us with a solution based on VHDL constructs,
and asking how to convert that solution to Verilog.  And unless
your tools support Verilog-2001 generates, you can't.  You can
handle some simple cases with `ifdef, but it can't be parameterized
for different instances during elaboration that way.

However, if you presented us with the problem you are trying
to solve, we might be able to suggest a solution based on
Verilog constructs.



Wed, 30 Nov 2005 06:04:33 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. VHDL generate statement in MG

2. CADENCE VHDL-XL 1.1 (Generate Statement)

3. VHDL-93 generates different concatenation results from VHDL-87

4. VHDL-93 generates different concatenation results from VHDL-87

5. ODBC and generated SQL statements

6. Generate SQL statements using Templates

7. generate statement

8. Equivalent of GENERATE Statement

9. Generate statement in verilog?

10. equivalent generate statement in verilog

11. GENERATE statement in verilog

12. generate statements

 

 
Powered by phpBB® Forum Software