divide by 4.5
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divide by 4.5

Is there a way to divide a clock by 4.5 in verilog?

That is, four full cycles and one half cycle.

Thanks for the response.

Tue, 04 Mar 2003 08:07:22 GMT
divide by 4.5

Quote:

> Is there a way to divide a clock by 4.5 in verilog?

> That is, four full cycles and one half cycle.

> Thanks for the response.

This code divides a clock by 4.5 with 2/2.5 duty cycles. Key is to
use two edges of the clock. It may have syntax errors for I am mostly
a VHDL writer.

John

// en is synchronously generated from the falling edge of clk
module(clk, en, dclk);
input clk, en;
output dclk;

reg dclk;

reg [3:0] counter1, counter2;
reg dclk1, dclk2;

begin
if (en == 1'b0)
counter1 = 4'b0000;
else if (counter1 == 4'b1000)
counter1 = 4'b 0;
else
counter1 = counter1 + 1;
end

begin
if (en == 1'b0)
counter2 = 4'b0000;
else if (counter2 == 4'b1000)
counter2 = 4'b 0;
else
counter2 = counter2 + 1;
end

begin
if (en == 1'b0)
dclk1 = 1'b0;
else if (counter1 == 4'b0000)
dclk1 = 1'b1;
else if (counter1 == 4'b0010)
dclk1 = 1'b0;
end

begin
if (en == 1'b0)
dclk2 = 1'b0;
else if (counter2 == 4'b0100)
dclk1 = 1'b1;
else if (counter1 == 4'b0110)
dclk1 = 1'b0;
end

begin
dclk = dclk1 | dclk2;
end

endmodule

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Wed, 05 Mar 2003 03:00:00 GMT
divide by 4.5
Thanks for the response .. John. Your code is similar to the type of
things I was attempting.  I found something simpler on the net that you
might be interested in .

http://www.ednmag.com/ednmag/reg/1997/052297/11di_05.htm#Listing 1

This shift register based implementation takes only few lines of code and
synthesizes without any problems.

//duty factor 1:3.5
module edn4_5(inclk,Reset,outclk);
input inclk;
input Reset;
output outclk;
reg [8:0] a;
reg b;

begin
if (Reset)  a = 9 'b 000000001;
else a = {a[7:0], a[8]} ;
end

begin
if (Reset)  b =0;
else b=a[4];
end

assign outclk = b|a[0] ;
endmodule

Sat, 08 Mar 2003 03:00:00 GMT
divide by 4.5
I think that code is little bit dangerous becase it can not recover by
itself.
I mean if register a is accidently changed to undesiable value, it would not
work well.

My another code is,

module clk_dbl(dbl_clk,clk);
input  clk;
output dbl_clk;
reg    dff;
assign dbl_clk = clk ^ dff;

dff <= clk;
endmodule

module dev4_5(dbl_clk,out_clk);
input  dbl_clk;
output out_clk;
reg [3:0] count;

if (count==8)
count <= 0;
else
count <= cout + 1;
assign out_clk = count[3];
endmodule

Hisashi Matsumoto

Quote:

> Thanks for the response .. John. Your code is similar to the type of
> things I was attempting.  I found something simpler on the net that you
> might be interested in .

> http://www.ednmag.com/ednmag/reg/1997/052297/11di_05.htm#Listing 1

> This shift register based implementation takes only few lines of code and
> synthesizes without any problems.

> //duty factor 1:3.5
> module edn4_5(inclk,Reset,outclk);
>  input inclk;
> input Reset;
> output outclk;
> reg [8:0] a;
> reg b;

>  begin
>  if (Reset)  a = 9 'b 000000001;
>  else a = {a[7:0], a[8]} ;
>  end

>  begin
>   if (Reset)  b =0;
>   else b=a[4];
>  end

> assign outclk = b|a[0] ;
>  endmodule

Fri, 14 Mar 2003 03:00:00 GMT

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