Final Call: BACUP: Verification, formal/physical, source link 
Author Message
 Final Call: BACUP: Verification, formal/physical, source link


           San Francisco, Silicon Valley Bay Area
                (Open to all Cadence Users)



1. Final Program of BACUP Meeting on Wednesday the 16th of October
   - Verification products and methodologies
   - Formal Verification, SourceLink

2. Invitation to a Cadence Seminar series,
   "From ASIC to System Chip - A Technology Forum"

3. Job openings at Apple and Tandem


1. BACUP Meeting:

Join us on Wednesday, October 16, 1996 at Cadence Design
Systems, Bldg. 5, Conference Center 2655 Seely Rd., San Jose,

We have an exciting afternoon for you beginning with lunch provided
by Cadence. With your continued input and support, we hope to make
the meetings a great place to network and learn from each other.

The theme topic is Verification strategies. Presenters include several
verification groups at Cadence: a talk by Jerry Burch of the Cadence
Berkeley labs on Formal Verification and a panel discussion on
Cadence's physical verification tools.

Daniel Chapiro of Systems Science and Eugene Zhang of Cisco Systems
will describe Systems Science's VERA high-level verification system.

We will also have an opportunity to discuss the latest and greatest in
Cadence's SourceLink.


THEME:      What's Cooking with Verification Products

HOT TOPICS:  Formal Verification, SourecLink

12:00           Lunch/Networking
                Light lunch provided by Cadence. IMPORTANT: Please RSVP

                specify if you will be joining us for lunch by Monday,
                October 14.

1:00            Welcome/Opening Remarks
                Shankar Hemmady, BACUP Chairperson

1:05            BACUP Business - Shankar Hemmady
                 -  Introducing the BACUP Vice-Chair
                 -  Job Listing Announcements

1:15            1996 International Cadence User Conference, User Viewpoints
                - Peggy Herrington, Intel Corporation
                - Mike Murray, Acuson Corporation

1:30            Cadence's Formal Verification Strategy
                Jerry Burch, Research Scientist, Cadence Berkeley Labs
                Jerry will describe some of Cadence's research in formal
                verification and how it can be most effectively used during

                Jerry and his colleagues at Cadence Berkeley Labs have offered
                all-day tutorials on advances in verification including
                formal verification and cycle-based simulation and timing
                analysis. There was one such tutorial at DAC '96 and there will
                be one more at ICCAD '96 in November in Santa Clara.

2:00            High Performance Verification - The Next Generation
                Cadence Physical Verification Product Engineering Team

               "This presentation and panel will include an update on Vampire,
                Cadence's breakthrough hierarchical verifier, and Cadence's
                Performance Verification solutions for extraction and
                analysis.  There will be members of the Product Engineering
                Team to answer questions after the presentation."

3:00            Refreshments Break and Raffle

3:15            Functional Verification of Verilog Designs with the VERA
                High-Level Verification System
                Daniel Chapiro, PhD., CEO, Systems Science
                Eugene Zhang, Verification Engineer, Cisco Systems

               "We will show how to generate compact but very exhaustive
                testbenches which are easily understandable and maintainable.  
                In our presentation we will discuss the functional
                verification of complex designs and present an efficient
                approach to fully self-checking testbenches. We will
                illustrate this using concurrent techniques in a transaction-
                based environment, to verify a switching system."

4:00            "What's New with SourceLink" Presentation and Demo
                Ed Haas, Sr. Information Delivery Staff, Cadence
                Highlighting 2 new capabilities available on its online
                technical support service
                *  Service Request/PCR Status Browser
                *  Vastly Improved Full-Text Search Capability

4:40            Adjourn

               If you would like to be added to our mailing list,  please

               For more information or directions to Cadence, please



This invitation is reproduced as is, courtesy of Cadence Design Systems.
For registration, call (800) 800-2700, send a fax (408) 894-2322, or

           "From ASIC to System Chip - A Technology Forum"

October 15                                      October 17
Renaissance Meeting                             Embassy Suites
5201 Great America                              9000 SW Washington Square Road
Santa Clara, CA 95054                           Tigard, OR  97223
408-562-6111                                    503-644-4000

For the first time in the electronics industry, the business requirements
of the semiconductor manufacturers align perfectly with those of the
systems companies. Both are looking at complex systems-on-a-chip as the
answer to increased pressures and customers' demands.

Cadence Design Systems cordially invites you to attend From ASIC to System
Chip, a technology forum that will explain the real impacts of the
system-chip revolution. We'll closely examine the strategies available to
help your company navigate the transition to a new deep submicron,
system-on-a-chip methodology - featuring mix-and-match IP; RTL prototyping;
and a complete timing-driven, deep submicron design flow. You'll hear how
leading ASIC foundries are changing their businesses, and what that means
for systems companies interested in improving their competitive edge.
You'll also have the opportunity to attend informative product
demonstrations that include:

** Silicon Ensemble -- Chip Assembly **
The ultimate solution to address significant IP content for
systems-in-silicon and deep submicron challenges, while providing a
low-risk vehicle for silicon delivery through capacity fluctuations and
rising complexity. Silicon Ensemble's simple automated environment
accelerates time-to-market and its comprehensive timing/ECO environment
minimizes design iterations.

** SiliconQuest -- Chip Planning **
 SiliconQuest demonstration shows timing-driven design flow targeted at
solving these deep submicron design issues. The demonstration will take a
0.5 micron, cell-based design through RTL floorplanning and estimation,
constraint management, timing analysis, synthesis, placement, and

** Agenda **
This forum is an intense one-day program that runs from 8:00 a.m. to 2:00
p.m., and includes a complimentary breakfast and lunch.

8:00 - 9:00 am       Registration & Continental Breakfast

9:00 - 9:15 am       Welcome/Introduction

9:15 - 10:15 am     Keynote: From ASIC to System-Chip
A combination of deep submicron technology and system-on-a-chip integration
is dramatically changing the working relationship between system houses and
merchant ASIC vendors. Find out how traditional ASIC vendors are adding
application-specific expertise to address the system-chip challenge and
what system companies need to do to be successful in this dynamic

10:15 - 10:30 am    Break

10:30 - 11:15 am    Riding the System-Chip Wave
A look at the opportunities and the challenges created by the rapid
emergence of system-on-a-chip ASIC designs. Covers strategies for making
the transition to a new "mix-and-match" design paradigm, including how to
best leverage the emerging third-party IP business.

11:15 - 12:00 am    RTL Prototyping and Constraint-Driven Design
Previous design methodologies are insufficient for deep submicron,
system-on-a-chip designs. This presentation looks at new design methods
that are critical to success in the system-chip era.

12:00 - 2:00 pm      Lunch and Product Demonstrations
Take a look at specific tools and technologies available to address deep
submicron ASIC design challenges. Demonstrations cover floorplanning,
timing estimation/analysis, datapath design, and chip assembly.

** Come and Join Us **

>From ASIC to System-Chip  is designed to provide useful information to

engineering professionals in wide range of industries. If you are an
engineering director, project leader, or CAD manager at a company designing
complex ASIC-based systems, this seminar will offer you the chance to
discuss future deep submicron and system-on-a-chip design methodologies,
and see demonstrations of new Cadence products that can be applied today to
tackle your design needs. Vice presidents of engineering, product line
managers, and other senior individuals are encouraged to attend the opening
keynote session to discover the unique business impacts of the
system-on-a-chip revolution, and to learn about strategies that can be
employed to help you better achieve your key business objectives.

** Registration **
Space is limited, so to guarantee your space at this informative technology
forum, please make your reservation today.

There are several ways you can register for this technology forum:
        calling us directly at (800) 800-2700,
        fax us at (408) 894-2322, or

When faxing or e-mailing your reservation, please make sure to include the
following information:

Mail Stop
City, State, Zip Code
E-mail address
Telephone number
Fax number
Primary business/technology interest
Breakout session you're interested in attending
Platform used:  ___  HP     ___  Sun      ___  Other

Nora Reichel
Sr. User Relations Specialist

(408) 944-7579
(408) 894-0233 Fax

Nora Reichel
Sr. User Relations Specialist

(408) 944-7579
(408) 894-0233 Fax


3. Job Openings:

   If your company has requirements for Cadence-literate people,  

   Please note that this is strictly for engineers and managers. We do not
   promote the use of the moderated mailing list for junk mail or as an
   advertising medium for professional recruiters.

The following job openings have been sent by the respective managers at Apple
and Tandem. Please respond directly to them.


The hardware development organization at Tandem Computers
in Cupertino, California is looking for a printed circuit
board (PCB) design tools expert.  Tandem is the market leader
in fault-tolerant computing for on-line transaction processing
and servers for enterprise computing.  We develop a variety
of ASICs and PCBs, including high-speed, dense PCBs using the
latest technologies.  Tandem is well known in Silicon Valley
for its excellent people and work environment.

We are looking for an individual to join a small team of people
that owns and drives our PCB design tools.  Responsibilities
range from supporting some of our current commercial and
home-brewed tools to improving our overall PCB design and
release processes by developing and or introducing new tools
and design methodology.

Qualifications:  BSEE/BSCS or equivalent;   at least three years
of industry experience;  good working knowledge of Unix
development environment (e.g., Perl, TCL);  in-depth familiarity
with PCB design processes and issues;  familiarity with some of
the major commercial PCB design tools (Concept, Allegro, CCT
preferred);  excellent {*filter*}and written communications skills.

If you meet these qualifications and get e{*filter*}d about
developing and supporting the design tools for state-of-the-art
PCB development in an excellent company, you are invited to
email your resume to:

Javad Khakbaz
Manager, Board & Systems Tools Department
Tandem Computers


Hello All,

My name is David Reha and I am the hiring manager for two positions;
an Allegro PCB designer and a Cadence  Applications Engineering, here
at Apple. If you are interested in either of these two opportunities,

send your resume to 6 Infinite Loop, MS 306-4CA, Cupertino CA, 95014.


David Reha

Following are job descriptions for each position:


Allegro PCB Designer

Responsible for assisting Engineers in the design and development of
complex, detailed layouts of printed circuit boards using Computer
Aided Design applications and related plotters and printers while
maintaining AppleB9s manufacturability design standards. Knowledge
of Cadence Allegro, basic UNIX commands plus experience in surface
mount design techniques and high density PCB design is essential.
Works on complex design assignments where independent action and a
high degree of initiative are required while following established
guidelines. Develops and documents new procedures for the design of
high density PCBB9s which are often on the B3critical pathB2 of a
project. Documents all design changes and maintains technical
coordination with Electrical, Test, EMC, Product Design and
Manufacturing Engineering.

Normally requires an AS degree plus 5 years equivalent experience or
a High school education plus seven years equivalent experience.


Cadence Applications Engineer

Responsible for integrating  design and analysis tools into the
system design process.  These responsibilities would include
integrating analysis and predictive CAD tools such as schematic
capture, logic simulation, static timing and signal integrity tools
into an evolving system design environment.  Requires skills in C,
UNIX and UNIX shell scripting, excellent debugging skills. Requires a
strong knowledge of Cadence CAD tools i.e. Concept, Allegro and
working with CAD data.  Strong communication skills and familiarity
of the system design process is a plus. BS EE/CS or equivalent job

Phone: (408) 974-1919

Tue, 30 Mar 1999 03:00:00 GMT  
 [ 1 post ] 

 Relevant Pages 

1. Final Call: BACUP: Verification, formal/physical, source link

2. BACUP meeting: Formal Verification, Physical Verification; SourceLink

3. BACUP meeting: Formal Verification, Physical Verification; SourceLink

4. Formal verification methods for OOPS

5. Formal methods for verification of OOPS

6. Functional programming languages & formal verification

7. IBM/Israel: Open Positions in Functional Formal Verification

8. Scientific puzzle of formal circuit verification at next week's DAC

9. Formal verification of one-hot state machine.

10. Formal Verification

11. Formal verification

12. Formal verification and Static Timing


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