Emacs verilog-mode part 1 of 2 
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 Emacs verilog-mode part 1 of 2

--
Here is my verilog-mode for emacs. It is a little rough in
spots. I am unable to complete this at this time. So maybe
Nels would like to pick it back up. I am posting it so that  
it may be of use to someone. Note this work is protected by
the GNU Copyleft agreement. I would appreciate any modifications
that anyone may make. See actual elisp code for more information.

THis code is submitted as a two part SHAR submission.

---- Cut Here and unpack ----
#!/bin/sh
# This is VERILOG.EL, a shell archive (shar 3.24)

# Source directory /home/eversole
#
# existing files WILL be overwritten
#
# This is part 1 of a multipart archive                                    
# do not concatenate these parts, unpack them in order with /bin/sh        
#
# This shar contains:
# length  mode       name
# ------ ---------- ------------------------------------------
#  63142 -rwxr-xr-x verilog.el
#
if touch 2>&1 | fgrep '[-amc]' > /dev/null
 then TOUCH=touch
 else TOUCH=true
fi
if test -r shar3_seq_.tmp; then
        echo "Must unpack archives in sequence!"
        next=`cat shar3_seq_.tmp`; echo "Please unpack part $next next"
        exit 1
fi
# ============= verilog.el ==============
echo "x - extracting verilog.el (Text)"
sed 's/^X//' << 'SHAR_EOF' > verilog.el &&
X;; Verilog  HDL mode, and its special commands.
X;;
X;; Created by Richard Eversole
X;; Cadence Design Systems
X;; Lowell MA
X;;
X;; Note while parts of this are better than any of the other
X;;   verilog modes I have found, this version is really more
X;;   of a work in progress. Unfortunately, situations dictate
X;;   that I discontinue my development efforts. Therefore,
X;;   I am releasing this code "AS-IS". Your mileage may vary
X;;   depending upon usage and code conditions.
X;;   <See running commentary in modification section for
X;;    a list of what I was trying to do and how far I may
X;;    have actually gotten.>
X;;
X;;=====================================================================
X;; Based upon the verilog mode of Anders Nordstrom
X;; This code is distributed under the GNU General Public
X;; license (Any version).
X;;                        NO WARRANTY
X;;
X;;  BECAUSE THIS SOFTWARE IS LICENSED FREE OF CHARGE, WE PROVIDE ABSOLUTELY
X;;NO WARRANTY, TO THE EXTENT PERMITTED BY APPLICABLE STATE LAW.  EXCEPT
X;;WHEN OTHERWISE STATED IN WRITING, RICHARD EVERSOLE AND/OR OTHER
X;;PARTIES PROVIDE THIS SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND,
X;;EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
X;;IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
X;;PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
X;;PROGRAM IS WITH YOU.  SHOULD THIS PROGRAM PROVE DEFECTIVE,
X;;YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
X;;
X;; (Short form: If it works good!, if it does not then you are SOL)
X;;
X;;=====================================================================
X;; Support:
X;; Basically you are on your own. However, I may attempt to
X;; fix any bugs, or add any enhancements that are requested.
X;; This code was developed on my own time and so any actual
X;; support is likely to be very limited.
X;;
X;; If you make any fixes or enhancements, I would like to
X;; have them as well. Please send them to:

X;;
X;; MODIFICATION HISTORY
X;; Date   Version Who, What & Why

X;;                Started from Anders Nordstrom's verilog-mode and
X;;                enhanced based on an ada-mode based version of
X;;                verilog-mode and a vhdl-mode from Todd Carpenter.
X;;                Added special conditional compilation block handlers
X;;                Changed header and modification comment sections
X;;                  marginally to better reflect Cadence styles.
X;;                  In process copyright block now boxed in a way
X;;                  that you can change it easily and it still should
X;;                  come out boxed.
X;;                Added many templates for Verilog HDL features.
X;;                  Template type approach choosen instead of
X;;                  trying and figure out useful keys. All templates
X;;                  use abbrev-hooked mode taken from Todd's vhdl-mode.
X;;                Reorganized code for easier maintainance. Moved all
X;;                  configuration items to top and grouped functions.
X;;                  Within some of the larger groups that deal directly
X;;                  with Verilog constructs I have order the functions
X;;                  alphabetically. Please maintain this ordering in
X;;                  any modifications you make.
X;;                Took some indentation commands from c++ mode by
X;;                  Dave Detlefs, Stewart Clamen, and Glenn Ditchfield.
X;;                  Since Verilog comments work like C++ comments this
X;;                  should make it easier to handle them.
X;;                Indentation still does not work right. (not even close)
X;;                In an attempt to get an indentation mode that works
X;;                  I have started over from the c-mode indentation
X;;                  functions.
X;;
X;;                Sorry folks. This is where I have to leave it.
X;;                Indentation does not really work but is closer.
X;;                The templates work.
X;;
X;;   Further work suggestions:
X;;
X;;   Correct verilog-mode doc string to really agree with what
X;;           is going on. It's close though.
X;;
X;;   Modify  module template to prompt for ports and port types
X;;          and the generate a better skeleton description.
X;;
X;;   Implement a true template mode that is much more flexible
X;;          than the hooked abbrev mode currently used.
X;;
X;;   Make indentation work!!!
X;;
X;;   Provide a way for the editor to keep track of symbols that
X;;       are defined within the current module. This is a much
X;;       fancier dynamic abbrev facility since it must be
X;;       scope aware.
X;;
X
X(provide 'verilog-mode)
X
X;; Customization section:
X;;   This is the simple customization section. The user can
X;;   change these variables/constants here or in there own
X;;   startup files.
X;;
X;; Here are some values the user is very likely to wish to
X;;  override:
X;;
X(defvar verilog-current-timescale "1ns/1ns"
X "*Timescale default value -- Used by verilog-header")
X
X(defvar verilog-company-name "Cadence Design Systems"
X "*Used by verilog-header to create comments")
X
X(defvar verilog-box-size 60
X "*Size of copyright box")
X
X;; Definition of various useful constants determining indentation
X;; of statements in Verilog HDL mode.
X
X(defconst verilog-indent-level 2
X "Indentation of Verilog HDL statements with respect to containing block.")
X(defconst verilog-begin-imaginary-offset 0
X "Imagined indentation of a Verilog begin that actually follows a statement.")
X(defconst verilog-begin 0
X "Extra indentation for begin and end, compared with other text in same context.")
X(defconst verilog-argdecl-indent 2
X "Indentation level of declarations of Verilog HDL function arguments.")
X(defconst verilog-label-offset -2
X "Offset of Verilog label lines and case statements relative to usual indentation.")
X(defconst verilog-continued-statement-offset 2
X "Extra indent for lines not starting new statements.")
X(defconst verilog-continued-begin-offset 0
X "Extra indent for substatements that start with begin.
XThis is in addition to verilog-continued-statement-offset.")
X
X;;
X;; Verilog gate template controls
X;;
X
X(defvar verilog-instance-name-base "U"
X  "* Base value of verilog instance name")
X(defconst verilog-instance-num 0
X  "Current verilog instance number")
X(defvar verilog-auto-name nil
X  "* Automatically name verilog primitives if t")
X(defvar verilog-model-strength nil
X  "* Include strength specifications on primitives if t")
X(defvar verilog-default-strength0 "strong0"
X  "* Default 0 strength of primitive gate output")
X(defvar verilog-default-strength1 "strong1"
X  "* Default 1 strength of primitive gate output")
X
X;;
X;; Other useful variables
X;;
X(defconst verilog-auto-newline t
X  "*Non-nil means automatically newline before and after braces,
X  and after colons and semicolons, inserted in Verilog HDL code.")
X
X(defconst verilog-tab-always-indent t
X    "*Non-nil means TAB in Verilog mode should always reindent the current line,
X    regardless of where in the line point is when the TAB command is used.")
X
X;;
X;; End simple customization
X;;
X;; The rest of this is the real code for verilog-mode
X;;
X
X;  This goes into your .abbrev_defs file, but if it isn't there, this takes
X;  care of adding it automatically.
X;;(defvar verilog-mode-abbrev-table nil
X;;  "Abbreviation table used in Verilog HDL mode buffers.")
X;;(define-abbrev-table 'verilog-mode-abbrev-table (
X;;))
X
X(makunbound 'verilog-mode-abbrev-table) ;; for certain debugging we need this
X
X(and (not (boundp 'verilog-mode-abbrev-table))
X     (file-exists-p abbrev-file-name)
X     (read-abbrev-file nil t)
X) ;if no table and abbrev file exists, read it
X
X(and (or (not (boundp 'verilog-mode-abbrev-table))
X        (not verilog-mode-abbrev-table)) ;if no table or it is nil, define it.
X    (define-abbrev-table 'verilog-mode-abbrev-table
X      '(
X;;
X;; Custom Verilog Abbrev Table
X;;
X        ("mon" "$monitor();" nil 0)
X;;
X;; timing checks with helpful comments
X;;
X        ("setup" "
X\t// $setup( data-event, reference_event, limit, <notifier>);
X\t// $setup( data, posedge clock, 50, setup_viol_flag);
X\t$setup();" nil 0)
X        ("hold" "
X\t// $hold( reference_event, data-event, limit, <notifier>);
X\t// $hold( posedge clock, data, 50, hold_viol_flag);
X\t$hold();" nil 0)
X        ("width" "
X\t// $width( [pos|neg]edge reference_event, limit, <threshold>, <notifier>);
X\t// $width( posedge clock, data, 50,0, width_viol_flag);
X\t$width();" nil 0)
X        ("period" "
X\t// $period( [pos|neg]edge reference_event, limit, <notifier>);
X\t// $period( posedge clock, data, 100, period_viol_flag);
X\t$period();" nil 0)
X        ("skew" "
X\t// $skew( reference_event, data-event, limit, <notifier>);
X\t// $skew( posedge clock1, posedge clock2, 5, skew_viol_flag);
X\t$skew();" nil 0)
X        ("recovery" "
X\t// $recovery( [pos|neg]edge reference_event, data-event, limit, <notifier>);
X\t// $recovery( posedge set, posedge clock, 5, recovery_viol_flag);
X\t$recovery();" nil 0)
X        ("setuphold" "
X\t// $setuphold( reference_event, data-event, setup-limit, hold-limit, <notifier>);
X\t// $setuphold( posedge clock, data, 5, 3, setuphold_viol_flag);
X\t// use of $setuphold is not recommended when combined with
X\t// conditioning events.
X\t$setuphold();" nil 0)
X;;
X;; Verilog HDL abbrevs
X;;
X
X;; Edge abbrevs
X
X        ("re" "edge[01,x1]" nil 0)
X        ("pe" "posedge" nil 0) ;; edge[01,0x,x1]
X        ("pose" "posedge" nil 0)
X        ("fe" "edge[10,1x]" nil 0)
X        ("ne" "negedge" nil 0) ;; edge[10,1x,x0]
X        ("nege" "negedge" nil 0)
X
X;;
X;; Verilog HDL structures
X;;
X
X        ("alw" "" verilog-always-hooked 0)
X        ("alwa" "" verilog-always-hooked 0)
X        ("alway" "" verilog-always-hooked 0)
X        ("always" "" verilog-always-hooked 0)
X
X        ("fo" "" verilog-for-hooked 0)
X        ("for" "" verilog-for-hooked 0)
X
X        ("fore" "" verilog-forever-hooked 0)
X        ("forev" "" verilog-forever-hooked 0)
X        ("foreve" "" verilog-forever-hooked 0)
X        ("forever" "" verilog-forever-hooked 0)
X
X        ("fork" "" verilog-fork-hooked 0)
X
X        ("ifb" "" verilog-if-block-hooked 0)
X        ("if" "" verilog-if-hooked 0)
X
X        ("ifd" "" verilog-ifdef-hooked 0)
X        ("ifs" "" verilog-ifdef-synth-hooked 0)
X
X        ("ini" "" verilog-initial-hooked 0)
X        ("init" "" verilog-initial-hooked 0)
X        ("initi" "" verilog-initial-hooked 0)
X        ("initia" "" verilog-initial-hooked 0)
X        ("initial" "" verilog-initial-hooked 0)
X
X        ("j" "join" nil 0)
X        ("jo" "join" nil 0)
X        ("joi" "join" nil 0)
X
X        ("mod" "" verilog-module-hooked 0)
X        ("modu" "" verilog-module-hooked 0)
X        ("modul" "" verilog-module-hooked 0)
X        ("module" "" verilog-module-hooked 0)
X
X        ("rep" "" verilog-repeat-hooked 0)
X        ("repe" "" verilog-repeat-hooked 0)
X        ("repea" "" verilog-repeat-hooked 0)
X        ("repeat" "" verilog-repeat-hooked 0)
X
X        ("wa" "" verilog-wait-event-control-hooked 0)
X        ("wai" "" verilog-wait-event-control-hooked 0)
X        ("wait" "" verilog-wait-event-control-hooked 0)
X
X        ("wh" "" verilog-while-hooked 0)
X        ("whi" "" verilog-while-hooked 0)
X        ("whil" "" verilog-while-hooked 0)
X        ("while" "" verilog-while-hooked 0)
X;;
X;;  Abbrevs to handle gate type primitives
X;;
X        ("and" "" (lambda () (verilog-primitive-hooked "and")) 0)
X        ("nand" "" (lambda () (verilog-primitive-hooked "nand")) 0)
X        ("nor" "" (lambda () (verilog-primitive-hooked "nor")) 0)
X        ("or" "" (lambda () (verilog-primitive-hooked "or")) 0)
X        ("xor" "" (lambda () (verilog-primitive-hooked "xor")) 0)
X        ("xnor" "" (lambda () (verilog-primitive-hooked "xnor")) 0)
X        ("buf" "" (lambda () (verilog-primitive-hooked "buf")) 0)
X        ("not" "" (lambda () (verilog-primitive-hooked "not")) 0)
X        ("bufif1" "" (lambda () (verilog-primitive-hooked "bufif1")) 0)
X        ("bufif0" "" (lambda () (verilog-primitive-hooked "bufif0")) 0)
X        ("notif1" "" (lambda () (verilog-primitive-hooked "notif1")) 0)
X        ("notif0" "" (lambda () (verilog-primitive-hooked "notif0")) 0)
X        ("nmos" "" (lambda () (verilog-primitive-hooked "nmos")) 0)
X        ("pmos" "" (lambda () (verilog-primitive-hooked "pmos")) 0)
X        ("rnmos" "" (lambda () (verilog-primitive-hooked "rnmos")) 0)
X        ("rpmos" "" (lambda () (verilog-primitive-hooked "rpmos")) 0)
X        ("cmos" "" (lambda () (verilog-primitive-hooked "cmos")) 0)
X        ("rcmos" "" (lambda () (verilog-primitive-hooked "rcmos")) 0)
X        ("tranif1" "" (lambda () (verilog-primitive-hooked "tranif1")) 0)
X        ("tranif0" "" (lambda () (verilog-primitive-hooked "tranif0")) 0)
X        ("rtranif1" "" (lambda () (verilog-primitive-hooked "rtranif1")) 0)
X        ("rtranif0" "" (lambda () (verilog-primitive-hooked "rtranif0")) 0)
X        ("tran" "" (lambda () (verilog-primitive-hooked "tran")) 0)
X        ("rtran" "" (lambda () (verilog-primitive-hooked "rtran")) 0)
X        ("pullup" "" (lambda () (verilog-primitive-hooked "pullup")) 0)
X        ("pulldown" "" (lambda () (verilog-primitive-hooked "pulldown")) 0)
X        ("udp" "" verilog-user-primitive-hooked 0)
X
X       );; table entries
X    ) ;; define table
X)
X
X
X(defvar verilog-mode-syntax-table ()
X  "Syntax table used in Verilog HDL mode buffers.")
X(if verilog-mode-syntax-table
X    ()
X  (setq verilog-mode-syntax-table (make-syntax-table))
X  (modify-syntax-entry ?\\ "\\" verilog-mode-syntax-table)
X  (modify-syntax-entry ?/ ". 14" verilog-mode-syntax-table)
X  (modify-syntax-entry ?* ". 23" verilog-mode-syntax-table)
X  (modify-syntax-entry ?+ "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?- "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?= "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?% "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?< "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?> "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?& "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?| "." verilog-mode-syntax-table)
X  (modify-syntax-entry ?\' "\"" verilog-mode-syntax-table))
X
X(defvar verilog-mode-map ()
X "Keymap used in Verilog HDL mode.")
X(if verilog-mode-map
X    ()
X  (setq verilog-mode-map (make-sparse-keymap))
X  (define-key verilog-mode-map "{" 'verilog-begin)
X  (define-key verilog-mode-map "}" 'verilog-end)
X  (define-key verilog-mode-map "\t" 'verilog-indent-command)
X  (define-key verilog-mode-map "\e\t" 'indent-relative)
X  (define-key verilog-mode-map "\es" 'center-line)
X  (define-key verilog-mode-map "\eS" 'center-paragraph)
X  (define-key verilog-mode-map "\e;" 'indent-for-comment)
X  (define-key verilog-mode-map "\177" 'backward-delete-char-untabify) ;DEL
X  (define-key verilog-mode-map "\e\C-h" 'mark-verilog-function)
X  (define-key verilog-mode-map "\e\C-q" 'indent-verilog-exp)
X  (define-key verilog-mode-map "\e{" 'verilog-paired-braces)
X  (define-key verilog-mode-map "\e[" 'verilog-paired-braces)
X  (define-key verilog-mode-map "\C-ch" 'verilog-header)
X  (define-key verilog-mode-map "\C-cm" 'verilog-modify-header)
X  (define-key verilog-mode-map "\C-c/" 'verilog-inline-comment)
X  (define-key verilog-mode-map "\C-cs" 'verilog-ifdef-synth)
X  (define-key verilog-mode-map "\C-cS" 'verilog-ifdef-synth-region)
X  (define-key verilog-mode-map "\C-ci" 'verilog-ifdef)
X  (define-key verilog-mode-map "\C-cI" 'verilog-ifdef-region)
X  (define-key verilog-mode-map "\C-xv" 'expand-abbrev)
X  (define-key verilog-mode-map ";"  'electric-verilog-semi)
X  (define-key verilog-mode-map ":"  'electric-verilog-terminator)
X  (define-key verilog-mode-map "\e#" 'verilog-delay-mtm )

X  (define-key verilog-mode-map "\C-c#" 'verilog-delay-mtm )

X)
X
X
X(defun verilog-mode ()
X  "Major mode for editing Verilog HDL code.  
X
XComments are delimited with /* and */. When running
Xindent-for-comment by typing ESC-; a comment is started in
Xthe position of the line determined by the variable comment-column
Xor directly after the line depending on the line length. You can
Xhit ESC-; anywhere on the line but the comment is always placed after
Xthe text in the line. Since indent-for-comment places both a begin
Xcomment and an end comment character, end of line comments starting
Xwith // is not supported.  
X
XInstead of typing begin and end use the {} keys and a begin or end
Xand a newline will be inserted. To insert { and } use ESC-{ which
Xinserts both { and } and leaves point between them. This works with
Xparanthesis as well.
X
XVerilog HDL Header: C-ch inserts a predefined header with information
Xabout designer, file name and creation date as the first entry in the
Xfile. This command also inserts module/endmodule commands and should
Xonly be used once, preferably on an empty file.
XWhen the file has been modified use verilog-modify-header to insert
Xa modification note with changes and date in the current header comment.
X
XSpecial commands:\\{verilog-mode-map}
X
XVariables controlling indentation style in Verilog HDL mode:
X verilog-tab-always-indent
X    Non-nil means TAB in Verilog HDL mode should always reindent the current line,
X    regardless of where in the line point is when the TAB command is used.
X verilog-auto-newline
X    Non-nil means automatically newline before and after begin/end,
X    and after colons and semicolons, inserted in Verilog code.
X verilog-indent-level
X    Indentation of Verilog statements within surrounding block.
X    The surrounding block's indentation is the indentation
X    of the line on which the begin appears.
X verilog-continued-statement-offset
X    Extra indentation given to a substatement, such as the
X    then-clause of an if or body of a while.
X verilog-continued-begin-offset
X    Extra indentation given to a begin that starts a substatement.
X    This is in addition to verilog-continued-statement-offset.
X verilog-begin
X    Extra indentation for line if it starts with a begin.
X verilog-begin-imaginary-offset
X    A Begin following other text is treated as if it were
X    this far to the right of the start of its line.
X verilog-argdecl-indent
X    Indentation level of declarations of verilog function and task arguments.
X verilog-label-offset
X    Extra indentation for line that is a label, or case or default.
X
XOther variables to control Verilog-mode:
X
X verilog-current-timescale
X    Defines the current timescale value used by verilog-header
X
XTemplates and Usage:
X
XA special template mode (based on abrev) has been implemented.
XTo expand a template press \C-xv (control-x v). This will
Xinvoke abbrev at the current point.
X
XTemplates are keyword expansions that will prompt you for
Xadditional information. The template mode implemented here
Xis not truly a template mode but a fancier abbreviation
Xexpansion. In the following descriptions items in \"<>\" are
Xoptional. That is
X    alw\C-xv  is the same as    alwa\C-xv  or alway\C-xv
X                    or always\C-xv
XItems in \"<<\" and \">>\" are prompted for during expansion.
X
XThe ... indicates where the point will be left after
Xexpansion.
X
XThe following template/abbrevs names are supported:
X

Xfo<r> - for (<<init>>,<<condition>>,<<step>>) ...;
Xfore<ver> - forever ...;
Xfork - fork ...; join
Xifb - if (<<condition>>) begin ...; end
Xif - if (<<condition>>) ...;
X
Xifd - `ifdef <<symbol>> ... `else `endif
Xifs - `ifdef SYNTH ... `else `endif
X
Xini<tial> - initial begin ... end
X
Xj<oin> - join ...
X
Xmod<ule> - module <<name>>(); ... endmodule
X
Xrep<eat> - repeat (<<count>>) ...;
X
Xwa<it> - wait (<<level event>>)
X
Xwh<ile> - while (<<condition>>) ...;
X
XIn addition there are templates for all of the
Xgate primitives in Verilog. Type the gate type name
Xfollowed by \C-xv and you will be prompted for all
Xof the signals on the gate. These templates also
Xuse the following variables to control there action:
X
Xverilog-instance-name-base  default U
X  Base value of verilog instance name
Xverilog-instance-num 0
X  Current verilog instance number
Xverilog-auto-name nil
X  Automatically name verilog primitives if t
Xverilog-model-strength nil
X  Include strength specifications on primitives if t
Xverilog-default-strength0   default strong0
X  Default 0 strength of primitive gate output
Xverilog-default-strength1   default strong1
X  Default 1 strength of primitive gate output
X
XTurning on verilog-mode calls the value of the variable verilog-mode-hook,
Xif that value is non-nil."
X  (interactive)
X  (kill-all-local-variables)
X  (setq selective-display t)
X  (setq selective-display-ellipses t)
X  (use-local-map verilog-mode-map)
X  (setq mode-name "Verilog")
X  (setq major-mode 'verilog-mode)
X  (setq local-abbrev-table verilog-mode-abbrev-table)
X  (set-syntax-table verilog-mode-syntax-table)
X  (make-local-variable 'paragraph-start)
X  (setq paragraph-start (concat "^$\\|" page-delimiter))
X  (make-local-variable 'paragraph-separate)
X  (setq paragraph-separate paragraph-start)
X  (make-local-variable 'paragraph-ignore-fill-prefix)
X  (setq paragraph-ignore-fill-prefix t)
X  (make-local-variable 'indent-line-function)
X  (setq indent-line-function 'indent-relative-maybe)
X  (make-local-variable 'indent-line-function)
X  (setq indent-line-function 'verilog-indent-line)
X  (make-local-variable 'require-final-newline)
X  (setq require-final-newline t)
X  (setq tab-width 8)  
X  (make-local-variable 'comment-start)
X  (setq comment-start "/* ")
X  (make-local-variable 'comment-end)
X  (setq comment-end " */")
X  (make-local-variable 'comment-column)
X  (setq comment-column 32)
X  (make-local-variable 'end-comment-column)
X  (setq end-comment-column 78)
X  (make-local-variable 'comment-start-skip)
X  (setq comment-start-skip "/\\*+ *")
X  (make-local-variable 'comment-indent-hook)
X  (setq comment-indent-hook 'verilog-comment-indent)
X  ;; Delete auto save file when file is saved for real if non-nil.
X  (make-local-variable 'delete-auto-save-files)
X  (setq delete-auto-save-files nil)
X  (make-local-variable 'parse-sexp-ignore-comments)
X  (setq parse-sexp-ignore-comments t)
X  (run-hooks 'verilog-mode-hook)
X)
X
X
X;;;
X;;; Centering Functions
X;;;
X
X(defun center-paragraph ()
X  "Center each line in the paragraph at or after point.
XSee center-line for more info."
X  (interactive)
X  (save-excursion
X    (forward-paragraph)
X    (or (bolp) (newline 1))
X    (let ((end (point)))
X      (backward-paragraph)
X      (center-region (point) end))))
X
X(defun center-region (from to)
X  "Center each line starting in the region.
XSee center-line for more info."
X  (interactive "r")
X  (if (> from to)
X      (let ((tem to))
X       (setq to from from tem)))
X  (save-excursion
X    (save-restriction
X      (narrow-to-region from to)
X      (goto-char from)
X      (while (not (eobp))
X       (center-line)
X       (forward-line 1)))))
X
X(defun center-line ()
X  "Center the line point is on, within the width specified by `fill-column'.
XThis means adjusting the indentation to match
Xthe distance between the end of the text and `fill-column'."
X  (interactive)
X  (save-excursion
X    (let (line-length)
X      (beginning-of-line)
X      (delete-horizontal-space)
X      (end-of-line)
X      (delete-horizontal-space)
X      (setq line-length (current-column))
X      (beginning-of-line)
X      (indent-to
X       (+ left-margin
X          (/ (- fill-column left-margin line-length) 2))))))
X
X;;;
X;;; Indentation Control
X;;;
X
X(defun electric-verilog-semi (arg)
X  "Insert character and correct line's indentation."
X  (interactive "P")
X  (if verilog-auto-newline
X      (electric-verilog-terminator arg)
X    (self-insert-command (prefix-numeric-value arg))))
X
X(defun electric-verilog-terminator (arg)
X  "Insert character and correct line's indentation."
X  (interactive "P")
X  (let (insertpos (end (point)))
X    (if (and (not arg) (eolp)
X            (not (save-excursion
X                   (beginning-of-line)
X                   (skip-chars-forward " \t")
X                   (or (= (following-char) ?#)
X                       ;; Colon is special only after a label, or case ....
X                       ;; So quickly rule out most other uses of colon
X                       ;; and do no indentation for them.
X                       (and (eq last-command-char ?:)
X                            (not (looking-at "case[ \t]"))
X                            (save-excursion
X                              (forward-word 1)
X                              (skip-chars-forward " \t")
X                              (< (point) end)))
X                       (progn
X                         (beginning-of-verilog-module)
X                         (let ((pps (parse-partial-sexp (point) end)))
X                           (or (nth 3 pps) (nth 4 pps) (nth 5 pps))))))))
X       (progn
X         (insert last-command-char)
X         (verilog-indent-line)
X         (and verilog-auto-newline
X              (not (verilog-inside-parens-p))
X              (progn
X                (newline)
X                (setq insertpos (- (point) 2))
X                (verilog-indent-line)))
X         (save-excursion
X           (if insertpos (goto-char (1+ insertpos)))
X           (delete-char -1)
X          )
X        )
X    )
X    (if insertpos
X       (save-excursion
X         (goto-char insertpos)
X         (self-insert-command (prefix-numeric-value arg))
X        )
X      (self-insert-command (prefix-numeric-value arg))
X    )
X  )
X)
X
X(defun verilog-comment-indent ()
X  "This is used by indent-for-comment to decide how much to indent
Xa comment in Verilog HDL code based on its context. "
X         ;; may need to handle //
X  (if (looking-at "^/\\*")      ; /* in the beginning of line.
X      0                                ;Existing comment at bol stays there.
X    (save-excursion
X      (skip-chars-backward " \t")       ; skip all tabs backwards
X      (max (1+ (current-column))       ;Else indent at comment column
X          comment-column))
X))     ; except leave at least one space.
X
X(defun verilog-indent-command (&optional whole-exp)
X  "Indent current line as Verilog HDL code, or in some cases insert
Xa tab character.
XIf verilog-tab-always-indent is non-nil (the default),
X       always indent current line.
X Else if point is at the left margin or in the line's indentation
X       indent the current line only
X Else  insert a tab.
X
XA numeric argument, regardless of its value,
X   means indent rigidly all the lines of the expression starting
X   after point so that this line becomes properly indented.
X
XThe relative indentation among the lines of the expression are preserved."
X  (interactive "P")
X  (if whole-exp
X      ;; If arg, always indent this line as Verilog HDL
X      ;; and shift remaining lines of expression the same amount.
X      (let ((shift-amt (verilog-indent-line))
X           beg end)
X       (save-excursion
X         (if verilog-tab-always-indent
X             (beginning-of-line))
X         (setq beg (point))
X         (forward-sexp 1)
X         (setq end (point))
X         (goto-char beg)
X         (forward-line 1)
X         (setq beg (point))
X        ) ;; save-excursion
X       (if (> end beg)
X           (indent-code-rigidly beg end shift-amt "#")))
X    (if (and (not verilog-tab-always-indent)
X            (save-excursion
X              (skip-chars-backward " \t")
X              (not (bolp))))
X       (insert-tab)
X      (verilog-indent-line)
X    )
X  ) ;; if whole-exp
X) ;; verilog-indent-command
X
X(defun verilog-inside-parens-p ()
X  (condition-case ()
X      (save-excursion
X       (save-restriction
X         (narrow-to-region (point)
X                           (progn (beginning-of-defun) (point))
X          )
X         (goto-char (point-max))
X         (= (char-after (or (scan-lists (point) -1 1) (point-min))) ?\()
X        )
X      )
X    (error nil)
X  )
X)
X
X;;;;;xxxxxx
X(defun verilog-indent-line ()
X  "Indent current line as Verilog HDL code.
XReturn the amount the indentation changed by."
X  (let ((indent (calculate-verilog-indent nil))
X       beg shift-amt
X       (case-fold-search nil)
X       (pos (- (point-max) (point))))
X    (beginning-of-line)
X    (setq beg (point))
X    (cond
X      ((eq indent nil)
X         (setq indent (current-indentation))
X      ) ;; ((eq...))
X
X      ((eq indent t)
X        (setq indent (calculate-verilog-indent-within-comment))
X      ) ;; ((eq ...)
X
X      ((looking-at "[ \t]*#")
X        (setq indent 0)
X      ) ;; ((looking-at ...))
X
X      (t
X        (skip-chars-forward " \t")
X        (if (listp indent) (setq indent (car indent)))
X        (cond
X          ((or (looking-at "case[ \t]")
X               (and (looking-at "[A-Za-z]")
X                 (save-excursion
X                   (forward-sexp 1)
X                   (looking-at ":")
X                 );; save-excursion
X               ) ;; and(looking-at ...)
X             ) ;; or(looking-at...)
X             (setq indent (max 1 (+ indent verilog-label-offset)))
X           );; ((or ...))
X
X           ((and (looking-at "else\b*")
X               (not (looking-at "else\s_")))
X               (setq indent (save-excursion
X                 (verilog-backward-to-start-of-if)
X                 (current-indentation))
X           )) ;; (and ...)
X
X           ((looking-at "endmodule")
X             (setq indent (- indent verilog-indent-level)
X           )) ;; ((looking-at ...)
X
X           ((looking-at "module")
X             (setq indent (+ indent verilog-begin-offset)
X           )) ;; ((looking-at ...)
X
X        ) ;; (cond ...)
X      ) ;; (t ...)
X
X    ) ;; (cond ...)
X
X    (skip-chars-forward " \t")
X    (setq shift-amt (- indent (current-column)))
X    (if (zerop shift-amt)
X      (if (> (- (point-max) pos) (point))
X           (goto-char (- (point-max) pos))
X      ) ;; (if (> ...))
X      (delete-region beg (point))
X      (indent-to indent)
X      ;; If initial point was within line's indentation,
X      ;; position after the indentation.  Else stay at same point in text.
X      (if (> (- (point-max) pos) (point))
X         (goto-char (- (point-max) pos))
X      ) ;; (if (> ...))
X    ) ;; (if (zerop...))
X  shift-amt) ;; (let ...)
X) ;; verilog-indent-line()
X
X;;xxxxx backwards search commands
X
X(defun verilog-backward-to-noncomment (lim)
X  (let (opoint stop)
X    (while (not stop)
X      (skip-chars-backward " \t\n\r\f" lim)
X      (setq opoint (point))
X      (cond
X        ((and (>= (point) (+ 2 lim))
X            (save-excursion
X             (forward-char -2)
X             (looking-at "\\*/")
X            ) ;; (save-excursion ...)
X          ) ;; (and (>= ...)
X          (search-backward "/*" lim 'move)
X        ) ;; ((and ...)
X
X        ((and
X          (search-backward "//" (max (point-bol) lim) 'move)
X          (not (within-string-p (point) opoint))
X        )) ;; ((and ...)
X
X        (t
X          (beginning-of-line)
X          (skip-chars-forward " \t")
X          (if (looking-at "#")
X           (setq stop (<= (point) lim))
X           (setq stop t)
X           (goto-char opoint)
X          );; (if ...)
X        ) ;; (t ...)
X      ) ;; (cond ...)
X    ) ;; (while ...)
X  ) ;; (let ...)
X) ;; verilog-backward-to-comment()
X
X(defun point-bol ()
X  "Returns the value of the point at the beginning of the current
X       line."
X  (save-excursion
X    (beginning-of-line)
X    (point)))
X
X(defun verilog-backward-to-start-of-continued-exp (lim)
X  (if (= (preceding-char) ?\))
X      (forward-sexp -1))
X  (beginning-of-line)
X  (if (<= (point) lim)
X      (goto-char (1+ lim)))
X  (skip-chars-forward " \t"))
X
X(defun verilog-backward-to-start-of-if (&optional limit)
X  "Move to the start of the last ``unbalanced'' if."
X  (or limit (setq limit (save-excursion (beginning-of-verilog-module) (point))))
X  (let ((if-level 1)
X       (case-fold-search nil))
X    (while (not (zerop if-level))
X      (backward-sexp 1) ;; need special check to be sure not in comment
X      (cond ((looking-at "else\b")
X            (setq if-level (1+ if-level)))
X           ((looking-at "if\b")
X            (setq if-level (1- if-level)))
X           ((< (point) limit)
X            (setq if-level 0)
X            (goto-char limit))))))
X
X(defun calculate-verilog-indent (&optional parse-start)
X  "Return appropriate indentation for current line as Verilog HDL code.
XIn usual case returns an integer: the column to indent to.
XReturns nil if line starts inside a string, t if in a comment."
X  (save-excursion
X    (beginning-of-line)
X    (let ((indent-point (point))
X         (case-fold-search nil)
X         state
X         containing-sexp)
X      (if parse-start
X         (goto-char parse-start)
X       (beginning-of-verilog-module)
X      ) ;; (if parse-start...)
X      (while (< (point) indent-point)
X       (setq parse-start (point))
X       (setq state (parse-partial-sexp (point) indent-point 0))
X       (setq containing-sexp (car (cdr state)))
X      ) ;; (while (<...))
X      (cond
X        ((or (nth 3 state) (nth 4 state))
X          ;; return nil or t if should not change this line
X          (nth 4 state)
X        ) ;; ((or ...))
X        ((null containing-sexp)
X          ;; Line is at top level.  May be data or function definition,
X          ;; or may be function argument declaration.
X          ;; Indent like the previous top level line
SHAR_EOF
echo "End of VERILOG.EL part 1"
echo "File verilog.el is continued in part 2"
echo "2" > shar3_seq_.tmp
exit 0

  =====================================================================


    Live long and prosper !



Mon, 05 Sep 1994 23:14:17 GMT  
 
 [ 1 post ] 

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