Signed and Unsigned numbers?

Quote:

> > How would you represent signed and unsigned numbers in Verilog?

You have to use the integer register type.

The reg is *always* unsigned.

Quote:

> And I also know how to describe following vhdl function into verilog

> function.

> entity MPY is

> Port ( A : In std_logic_vector (23 downto 0);

> B : In std_logic_vector (19 downto 0);

> MULOUT : Out std_logic_vector (23 downto 0) );

> end MPY;

> architecture BEHAVI{*filter*}of MPY is

> signal tpreg : signed(43 downto 0);

> begin

> tpreg <= signed(a)*signed(b);

> process( tpreg )

> begin

> mulout <= conv_std_logic_vector( tpreg(42 downto 19),24 );

> end process;

> end BEHAVIORAL;

module MPY(A, B, MULOUT);

input [23:0] A;

input [19:0] B;

output [23:0] MULOUT;

reg [23:0] MULOUT;

begin: BEH

integer INT_A;

integer INT_B;

reg [42:0] TPREG;

// convert the inputs to signed integers

INT_A = A;

INT_B = B;

// If their MSB is set, they contained a negative number...

if (A[23] = 1'b1) INT_A = INT_A - 24'hFFFFFF;

if (B[19] = 1'b1) INT_B = INT_B - 20'hFFFFF;

TPREG = INT_A * INT_B;

MULOUT = TPREG[42:19];

end

endmodule

Efficient synthesizability is another issue...