Signed and Unsigned numbers? 
Author Message
 Signed and Unsigned numbers?

Hello,

How would you represent signed and unsigned numbers in Verilog?  I know
that it is possible in  VHDL, but how would you do it in Verilog?


Thanks
Dan



Mon, 09 Jul 2001 03:00:00 GMT  
 Signed and Unsigned numbers?

Quote:

> Hello,
> How would you represent signed and unsigned numbers in Verilog?  I know
> that it is possible in  VHDL, but how would you do it in Verilog?

>  Thanks
> Dan

 Hi, everyone !
  And I also know how to describe following vhdl function into verilog
function.

entity MPY is
      Port (       A : In    std_logic_vector (23 downto 0);
                   B : In    std_logic_vector (19 downto 0);
              MULOUT : Out   std_logic_vector (23 downto 0) );
end MPY;

architecture BEHAVI{*filter*}of MPY is
   signal tpreg : signed(43 downto 0);
 begin
   tpreg <= signed(a)*signed(b);
   process( tpreg )
   begin
       mulout <= conv_std_logic_vector( tpreg(42 downto 19),24 );
   end process;
end BEHAVIORAL;

Solution to above question might be helpfule me in design.
Your comments are deeply appretiated.

Thanks,
Soo  Bon.



Mon, 09 Jul 2001 03:00:00 GMT  
 Signed and Unsigned numbers?

Quote:


> > Hello,
> > How would you represent signed and unsigned numbers in Verilog?  I know
> > that it is possible in  VHDL, but how would you do it in Verilog?

> >  Thanks
> > Dan

>  Hi, everyone !
>   And I also know how to describe following vhdl function into verilog
> function.

> entity MPY is
>       Port (       A : In    std_logic_vector (23 downto 0);
>                    B : In    std_logic_vector (19 downto 0);
>               MULOUT : Out   std_logic_vector (23 downto 0) );
> end MPY;

> architecture BEHAVI{*filter*}of MPY is
>    signal tpreg : signed(43 downto 0);
>  begin
>    tpreg <= signed(a)*signed(b);
>    process( tpreg )
>    begin
>        mulout <= conv_std_logic_vector( tpreg(42 downto 19),24 );
>    end process;
> end BEHAVIORAL;

> Solution to above question might be helpfule me in design.
> Your comments are deeply appretiated.

> Thanks,
> Soo  Bon.

Hello,

Maybe I am not understanding the statements made above.  How would I
represent signed and unsigned numbers in Verilog?


Dan



Mon, 09 Jul 2001 03:00:00 GMT  
 Signed and Unsigned numbers?

Quote:


> > How would you represent signed and unsigned numbers in Verilog?

You have to use the integer register type.
The reg is *always* unsigned.

Quote:
>   And I also know how to describe following vhdl function into verilog
> function.

> entity MPY is
>       Port (       A : In    std_logic_vector (23 downto 0);
>                    B : In    std_logic_vector (19 downto 0);
>               MULOUT : Out   std_logic_vector (23 downto 0) );
> end MPY;

> architecture BEHAVI{*filter*}of MPY is
>    signal tpreg : signed(43 downto 0);
>  begin
>    tpreg <= signed(a)*signed(b);
>    process( tpreg )
>    begin
>        mulout <= conv_std_logic_vector( tpreg(42 downto 19),24 );
>    end process;
> end BEHAVIORAL;

module MPY(A, B, MULOUT);
input  [23:0] A;
input  [19:0] B;
output [23:0] MULOUT;

reg [23:0] MULOUT;

begin: BEH
   integer INT_A;
   integer INT_B;
   reg [42:0] TPREG;

   // convert the inputs to signed integers
   INT_A = A;
   INT_B = B;
   // If their MSB is set, they contained a negative number...
   if (A[23] = 1'b1) INT_A = INT_A - 24'hFFFFFF;
   if (B[19] = 1'b1) INT_B = INT_B - 20'hFFFFF;

   TPREG = INT_A * INT_B;
   MULOUT = TPREG[42:19];
end

endmodule

Efficient synthesizability is another issue...



Mon, 09 Jul 2001 03:00:00 GMT  
 Signed and Unsigned numbers?
For synthesizable stuff (e.g. REGs and WIREs), everything is unsigned.
Are you asking for tricks to do 2's complement math (e.g. signed)
given you have only generic unsigned vectors?  We could all probably
start a little list of them, which is really just basic digital math.
Tricks like; how to do sign extension, how to negate a number,
adding/subtracting, how to do ABS, etc. etc.
Quote:
>Hello,

>How would you represent signed and unsigned numbers in Verilog?  I know
>that it is possible in  VHDL, but how would you do it in Verilog?


>Thanks
>Dan



Tue, 10 Jul 2001 03:00:00 GMT  
 Signed and Unsigned numbers?

Quote:

> Hello,

> How would you represent signed and unsigned numbers in Verilog?  I know
> that it is possible in  VHDL, but how would you do it in Verilog?


> Thanks
> Dan

  In verilog a reg and net type is interpreted as an unsigned number.
  EX:  module adder(A, B, C);
               input A, B;
               output R;

               assign R = A + B; // The operands are of net type
           endmodule

  EX: -4'd4 (-4 is represented in 2's complement using 4 bits).

   AND

   An integer type is interpreted as a signed number in 2's complement
form with the rightmost bit being the LSB.
   EX: 20 (20 - This is a 32 bit decimal number by default)
           -123 (This is a 32 bit decimal number in 2's complement by
default)

   The same rules apply when you have to synthesize these operators.

Regards -- Subbu

  vcard.vcf
< 1K Download


Sat, 14 Jul 2001 03:00:00 GMT  
 
 [ 6 post ] 

 Relevant Pages 

1. Newbie question......Unsigned and signed numbers

2. Force numbers as signed or unsigned

3. unsigned word to signed word in RB

4. Signed/Unsigned Documentation CW2.002

5. signed,unsigned in verilog?!

6. Signed/Unsigned Operations for OVI 2.0

7. Signed and unsigned

8. Signed / Unsigned question.

9. unsigned ,signed how does it works

10. More signed/unsigned arithmetic craziness

11. Numeric STD Signed/Unsigned/Extra

12. signed/unsigned v.s. integer

 

 
Powered by phpBB® Forum Software