`ifdef 
Author Message
 `ifdef

Easy,

Enclose the code in a "generate" that you can evaluate to true or
false...

Sorry no handy example.

--James

Quote:

> Hi,

> Does anyone know a comparable command for `ifdef in VHDL?

> Thanks in advance.

> --cameron

> --
> Cameron

> http://www.{*filter*}ramp.net/

--
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  Verilog Instructor        
  Author "Verilog Quickstart" ISBN 0-7923-9927-7
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Sat, 15 Jan 2000 03:00:00 GMT  
 `ifdef

Quote:

> Easy,

> Enclose the code in a "generate" that you can evaluate to true or
> false...

> Sorry no handy example.

> --James


> > Hi,

> > Does anyone know a comparable command for `ifdef in VHDL?

> > Thanks in advance.

What about this one:

     G2 : if (i=0) GENERATE
       x : PROCESS
        begin
        end process;
     END GENERATE G2;

     G3 : if (i>0) GENERATE
       pipe_reg_tmp_din1_0: reg
            GENERIC MAP(width1)
            PORT MAP(clk, tmp_din1_0(i-1), tmp_din1_0(i));
       pipe_reg_tmp_din1_1: reg
            GENERIC MAP(width1)
            PORT MAP(clk, tmp_din1_1(i-1), tmp_din1_1(i));
     END GENERATE G3;

/THomas
-------------------------------------------------
Thomas Johansson, teaching assistant
Electronics Systems, LiTH




Tue, 18 Jan 2000 03:00:00 GMT  
 
 [ 2 post ] 

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