Verilog-XL question (important)! 
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 Verilog-XL question (important)!

Quote:

> when I do the same for the top most
> level module ( shown below), it doesnt create a template. I do get the
> following message(one of the many other messages):

> *Error* eval: unbound variable - hnlVerilogBusesDone

> Is this a problem with my code(something to do with the port map?) or
> Verilog XL?

This is a Cadence internal error.  I don't believe anyone other than
those whose created it.  The culprit is in the screwballs call OSS,
HNL, and bus netlisting (aka {*filter*}betlisting in cadence).

This problem has nothing to do with Verilog language or simulation,
your only choice is to call Cadence for help.

tan



Sun, 10 Oct 1999 03:00:00 GMT  
 
 [ 1 post ] 

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