time division multiplexing in veriog 
Author Message
 time division multiplexing in veriog

I would like to TDM two signals, X and Y using verilog.
This incorporate a sync and idle signal.  Each of these signals
runs at 10 khz and I would like to TDM them into one 20 mhz
signal.

Can this be done within a simple mux or does in require a more
detailed design?

Thanks

DRW

* Sent from RemarQ http://www.*-*-*.com/ The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!



Fri, 26 Jul 2002 03:00:00 GMT  
 time division multiplexing in veriog
Iit will be helpful if you give the specs.
Well, in general it is possible to use a simple mux and
you will need a 40MHz signal to deocde your sync and idle.

-naveen


Quote:

> I would like to TDM two signals, X and Y using verilog.
> This incorporate a sync and idle signal.  Each of these signals
> runs at 10 khz and I would like to TDM them into one 20 mhz
> signal.

> Can this be done within a simple mux or does in require a more
> detailed design?

> Thanks

> DRW

> * Sent from RemarQ http://www.remarq.com The Internet's Discussion
Network *
> The fastest and easiest way to search and participate in Usenet -
Free!

Sent via Deja.com http://www.deja.com/
Before you buy.


Sat, 27 Jul 2002 03:00:00 GMT  
 time division multiplexing in veriog
I would think you would need some kind of a synchronization signal
when you extract sync and idle back from the 20MHz signal, unless
the "sync" signal you specify is your synchronization signal.

--eswar

: I would like to TDM two signals, X and Y using verilog.
: This incorporate a sync and idle signal.  Each of these signals
: runs at 10 khz and I would like to TDM them into one 20 mhz
: signal.

: Can this be done within a simple mux or does in require a more
: detailed design?

: Thanks

: DRW

: * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
: The fastest and easiest way to search and participate in Usenet - Free!



Sun, 28 Jul 2002 03:00:00 GMT  
 
 [ 3 post ] 

 Relevant Pages 

1. Veriog Simulator with GUI and Synthesis

2. using acc_handle_object on encrypted veriog netlist

3. Decoding an analog multiplexed signal

4. OT - Multiplexing Vehicle networks...

5. Measuring frequency, software multiplexing

6. Multiplexing Question

7. Multiplexed Address/Data Bus

8. How to multiplex the external clock correctly?

9. Clock multiplexing

10. Use of BUFT for Multiplexing 2:1

11. Multiplexing of adder during synthesize

12. clock multiplexing?

 

 
Powered by phpBB® Forum Software