verilog, Verilog model of Xilinx macro in VHDL Testbench fails

Verilog model of Xilinx macro in VHDL Testbench fails

Author	Message
Utku Ozca #1 / 7	Verilog model of Xilinx macro in VHDL Testbench fails Can I simulate a Verilog model of a RAMB4_S8_S8 element of Virtex-E in a VHDL testbench? Not succeeded in that yet. RAMB4_S8_S8 is in $XILINX/verilog/src/unisims and this Verilog code requires $XILINX/verilog/src/glbl.v to be compiled correctly. In typical Verilog testbench following must be done: glbl my_glbl (); In VHDL, its equivalent I can figure out would be: my_glbl : glbl; But when I choose "Design->Load Design..." and architecture of VHDL testbench, Modelsim tells me that it cannot resolve glbl in glbl.GSR assignment in RAMB4_S8_S8 element, although I had compiled it into work library. The reason why I have use Verilog models of Xilinx macros instantiated in VHDL testbench is that there are plenty of VHDL codes which call Xilinx macros. VHDL models can be used by using: LIBRARY UNISIM; USE UNISIM.all; ... which are not typed in original VHDL codes. But if I do it, then Synplify will be angry with that, because it will try to compile VHDL simulation models of Xilinx macros, which is nonsense. Is it possible to use LIBRARY and USE constructs with GENERATE?: IF SIMULATION=TRUE GENERATE LIBRARY UNISIM; USE UNISIM.all; END IF; Utku
Sat, 12 Jul 2003 01:04:18 GMT

Chris Dunla #2 / 7	Verilog model of Xilinx macro in VHDL Testbench fails Search for a file called glbl.v in your xilinx folder and compile that. Then when you laod your design, include glbl in the load. I don't use verilog too much these days so I don't remember the syntax something like vlog glbl.v vsim work glbl top of course with any other switches and what not which I don't remember right now. If you still have trouble I can look up that syntax. Chris Quote: > Can I simulate a Verilog model of a RAMB4_S8_S8 element of > Virtex-E in a VHDL testbench? Not succeeded in that yet. > RAMB4_S8_S8 is in $XILINX/verilog/src/unisims and this Verilog > code requires $XILINX/verilog/src/glbl.v to be compiled correctly. > In typical Verilog testbench following must be done: > glbl my_glbl (); > In VHDL, its equivalent I can figure out would be: > my_glbl : glbl; > But when I choose "Design->Load Design..." and architecture > of VHDL testbench, Modelsim tells me that it cannot resolve > glbl in glbl.GSR assignment in RAMB4_S8_S8 element, although > I had compiled it into work library. > The reason why I have use Verilog models of Xilinx macros instantiated > in VHDL testbench is that there are plenty of VHDL codes which call > Xilinx macros. > VHDL models can be used by using: > LIBRARY UNISIM; > USE UNISIM.all; > ... which are not typed in original VHDL codes. But if I do it, then > Synplify will be angry with that, because it will try to compile > VHDL simulation models of Xilinx macros, which is nonsense. > Is it possible to use LIBRARY and USE constructs with GENERATE?: > IF SIMULATION=TRUE GENERATE > LIBRARY UNISIM; > USE UNISIM.all; > END IF; > Utku
Sat, 12 Jul 2003 02:28:30 GMT

Utku Ozca #3 / 7	Verilog model of Xilinx macro in VHDL Testbench fails Quote: > Search for a file called glbl.v in your xilinx folder and compile that. > Then when you laod your design, include glbl in the load. > I don't use verilog too much these days so I don't remember the syntax > something like > vlog glbl.v > vsim work glbl top > of course with any other switches and what not which I don't remember > right now. > If you still have trouble I can look up that syntax. > Chris Chris, in my mail I had stated that glbl.v had already been compiled. Now I have learned that it is impossible to use the VHDL equivalent of the following Verilog construct which is necessary for verification with Xilinx macros: glbl global (); ...because in Modelsim (the simulator I'm using, which I have forgotten to mention it) it is impossible to instantiate Verilog models, which do not have terminals, within VHDL code. The only solution I have found is to modify the Verilog models of the macros, which lets me get rid of using glbl.v. Following example is for RAMB4_* elements in Xilinx UNISIM library: tri0 GSR = RSTA \| RSTB; /* instead of tri0 GSR = glbl.GSR ; */ This was a Modelsim-related problem. I'm still waiting for a concise answer for my previous question about Modelsim Utku
Sat, 12 Jul 2003 14:27:59 GMT

apeter #4 / 7	Verilog model of Xilinx macro in VHDL Testbench fails Quote: > Can I simulate a Verilog model of a RAMB4_S8_S8 element of > Virtex-E in a VHDL testbench? Not succeeded in that yet. > RAMB4_S8_S8 is in $XILINX/verilog/src/unisims and this Verilog > code requires $XILINX/verilog/src/glbl.v to be compiled correctly. > In typical Verilog testbench following must be done: > glbl my_glbl (); > In VHDL, its equivalent I can figure out would be: > my_glbl : glbl; > But when I choose "Design->Load Design..." and architecture > of VHDL testbench, Modelsim tells me that it cannot resolve > glbl in glbl.GSR assignment in RAMB4_S8_S8 element, although > I had compiled it into work library. > The reason why I have use Verilog models of Xilinx macros instantiated > in VHDL testbench is that there are plenty of VHDL codes which call > Xilinx macros. > VHDL models can be used by using: > LIBRARY UNISIM; > USE UNISIM.all; > ... which are not typed in original VHDL codes. But if I do it, then > Synplify will be angry with that, because it will try to compile > VHDL simulation models of Xilinx macros, which is nonsense. > Is it possible to use LIBRARY and USE constructs with GENERATE?: > IF SIMULATION=TRUE GENERATE > LIBRARY UNISIM; > USE UNISIM.all; > END IF; The easiest thing to do is to add a directive to your code. For Synplify, do the following: -- synthesis translate_off library unisim; use unisim.all; -- synthesis translate_on Voila. The synthesis tool will ignore the library clause and do the right thing, and the simulator will use the library and do the right thing. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."
Sun, 13 Jul 2003 02:35:09 GMT

Utku Ozca #5 / 7	Verilog model of Xilinx macro in VHDL Testbench fails Quote: > The easiest thing to do is to add a directive to your code. For > Synplify, do the following: > -- synthesis translate_off > library unisim; > use unisim.all; > -- synthesis translate_on > Voila. The synthesis tool will ignore the library clause and do the > right thing, and the simulator will use the library and do the right > thing. Yes, Andy, this is one of the best workarounds. But there are hundreds of VHDL codes, which we wouldn't touch them, if possible. Modification of 4 Verilog models of Xilinx macros was much easier than to update hundreds of VHDL code according to the method above. Utku
Sun, 13 Jul 2003 16:02:54 GMT

Ray Andrak #6 / 7	Verilog model of Xilinx macro in VHDL Testbench fails If the translate_on off is too much to add, you could remap the unisim library to the synplicity virtex library in synplicity. Quote: > > The easiest thing to do is to add a directive to your code. For > > Synplify, do the following: > > -- synthesis translate_off > > library unisim; > > use unisim.all; > > -- synthesis translate_on > > Voila. The synthesis tool will ignore the library clause and do the > > right thing, and the simulator will use the library and do the right > > thing. > Yes, Andy, this is one of the best workarounds. But there are > hundreds of VHDL codes, which we wouldn't touch them, > if possible. > Modification of 4 Verilog models of Xilinx macros was much > easier than to update hundreds of VHDL code according > to the method above. > Utku -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 http://www.andraka.com or http://www.fpga-guru.com
Sun, 13 Jul 2003 21:46:11 GMT

Utku Ozca #7 / 7	Verilog model of Xilinx macro in VHDL Testbench fails Quote: > If the translate_on off is too much to add, you could remap the unisim > library to the synplicity virtex library in synplicity. As I stated in my first posting in this thread, neither LIBRARY UNISIM; USE UNISIM.all; nor --synthesis translate_on LIBRARY UNISIM; USE UNISIM.all; --synthesis translate_off "or nor" any combination of both existed in VHDL codes. That means, VHDL codes have been designed for synthesis, but not for any kind of simulation. In order to get rid of any update of any combination of both above, because there are hundreds of VHDL codes, we have updated _only_ the Verilog macros which are called from within $XILINX/verilog/src/unisims to another directory. Utku
Mon, 14 Jul 2003 00:30:36 GMT

Page 1 of 1

[ 7 post ]