
Verilog model of Xilinx macro in VHDL Testbench fails
Quote:
> Can I simulate a Verilog model of a RAMB4_S8_S8 element of
> Virtex-E in a VHDL testbench? Not succeeded in that yet.
> RAMB4_S8_S8 is in $XILINX/verilog/src/unisims and this Verilog
> code requires $XILINX/verilog/src/glbl.v to be compiled correctly.
> In typical Verilog testbench following must be done:
> glbl my_glbl ();
> In VHDL, its equivalent I can figure out would be:
> my_glbl : glbl;
> But when I choose "Design->Load Design..." and architecture
> of VHDL testbench, Modelsim tells me that it cannot resolve
> glbl in glbl.GSR assignment in RAMB4_S8_S8 element, although
> I had compiled it into work library.
> The reason why I have use Verilog models of Xilinx macros instantiated
> in VHDL testbench is that there are plenty of VHDL codes which call
> Xilinx macros.
> VHDL models can be used by using:
> LIBRARY UNISIM;
> USE UNISIM.all;
> ... which are not typed in original VHDL codes. But if I do it, then
> Synplify will be angry with that, because it will try to compile
> VHDL simulation models of Xilinx macros, which is nonsense.
> Is it possible to use LIBRARY and USE constructs with GENERATE?:
> IF SIMULATION=TRUE GENERATE
> LIBRARY UNISIM;
> USE UNISIM.all;
> END IF;
The easiest thing to do is to add a directive to your code. For
Synplify, do the following:
-- synthesis translate_off
library unisim;
use unisim.all;
-- synthesis translate_on
Voila. The synthesis tool will ignore the library clause and do the
right thing, and the simulator will use the library and do the right
thing.
-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u
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