Name collision rules 
Author Message
 Name collision rules

Hi,

I have a question regarding name collisions in Verilog.  Is it legal
for a net or port of a module to have the same name as an instance
in that same module?  For example, is the following legal:

module names(in, out);
  input in;
  output out;

  blah out (in, out);

endmodule

Finally, if there are any such rules, are they documented in the LRM?

Thanks,

Mark



Mon, 16 Aug 1999 03:00:00 GMT  
 Name collision rules

Quote:

> Hi,

> I have a question regarding name collisions in Verilog.  Is it legal
> for a net or port of a module to have the same name as an instance
> in that same module?  For example, is the following legal:

> module names(in, out);
>   input in;
>   output out;

>   blah out (in, out);

> endmodule

> Finally, if there are any such rules, are they documented in the LRM?

> Thanks,

> Mark

------------------------------------------

If you are using Verilog-Xl, you will get
error message for this.
I am not sure if this is a rule but in general,
this is not a good modeling practise.

jeetendra




Tue, 17 Aug 1999 03:00:00 GMT  
 Name collision rules

Quote:

> Hi,

> I have a question regarding name collisions in Verilog.  Is it legal
> for a net or port of a module to have the same name as an instance
> in that same module?  For example, is the following legal:

> module names(in, out);
>   input in;
>   output out;

>   blah out (in, out);

> endmodule

> Finally, if there are any such rules, are they documented in the LRM?

> Thanks,

> Mark

In Verilog -XL It gives error as follows.

Compiling source file "collpse.v"

Error!    Element instance name (out) previously declared   [Verilog-EINPD]    
          "collpse.v", 5:
1 error

---
LRM does not talk explicitely about such case.

        Rajesh

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Tue, 17 Aug 1999 03:00:00 GMT  
 
 [ 3 post ] 

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