SNUG Europe Advanced Notice & CFP 
Author Message
 SNUG Europe Advanced Notice & CFP

                -------------------------------------
                          SNUG EUROPE 1994

                 ADVANCE NOTICE and CALL FOR PAPERS
                -------------------------------------

Third Meeting, September 20-21, Grenoble, France

The Third Annual Synopsys European Users Group Conference (SNUG Europe) will
 take place this year in Grenoble on Tuesday and Wednesday, September 20/21
 during EURO-DAC with EURO-VHDL 1994.

SNUG Europe provides you with the opportunity to meet other Synopsys users
 and share application ideas and experiences on your use of Synopsys
 High-Level Design tools.   You will also have the chance to make an impact
 on the development and direction of Synopsys technology by meeting and
 discussing your methodology and tools needs with Synopsys managers,
 research and development engineers and applications engineers.

SNUG Europe '94 will be held at the  Hotel President in Grenoble.  This
 year, the conference opens on the morning of the 20th after the EURO-DAC
 with EURO-VHDL '94 opening conference session.   It continues throughout
 the day concluding with the traditional quality party in the evening.  The
 tutorial sessions will be held the next morning in the Hotel President.

Please note that EURO-DAC with EURO-VHDL '94 runs in Grenoble from September
 19-23.  This event promises to build on the last two year's success with a
 strong conference and tutorial programme, large vendor exhibition and
 additional EDA events.   Justify your trip to SNUG Europe with the added
 value of EURO-DAC and EURO-VHDL conference  and exhibition participation.

CONFERENCE PROGRAMME

Last year you told us that the informal interaction with other Synopsys
 users was a valuable element of SNUG, we will therefore be hosting  a
 dinner and party again at the end of the day.  In addition, you also told
 us you needed more in-depth information on Synopsys methodologies and flows
 to silicon.  This year we will be offering three tutorials and a new
 Semiconductor Partner Design Flow track to complement the interactive user
 sessions.   Please see the accompanying Call for Papers below for session
 details and information on how to contribute and participate.

AGENDA

  TUESDAY 20th - SNUG EUROPE CONFERENCE
  11.30-13.0
    Registration & Buffet Lunch
  13.00-14.00
    Welcome and Keynote Address
    Synopsys Executive Q&A
  14.00-15.30
    Session 1 - 3 Concurrent Breakouts
      1A  Design Productivity
      1B  Tool Productivity
      1C  Semiconductor Partner Design Flow & Support
  16.00-17.30
    Session 2 - 3 Concurrent Breakouts Continue
      2A  Design Productivity
      2B  Tool Productivity
      2C  Semiconductor Partner Design Flow & Support
  19.00-Late
    SNUG Europe Party

  WEDNESDAY 21st - SNUG EUROPE TUTORIALS
  8.30-9.00
    Tutorial Registration
  9.00-12.00
    Tutorial A
    VHDL Coding Tricks and Techniques
  Tutorial B
    Advanced HDL Methodology
  Tutorial C
    "Pins-Out" Design Verification

Registration for the conference and optional tutorials will include lunch,
 refreshments, dinner and party on Tuesday 20th and refreshments on the 21st
 during the tutorials.  Registration will cost FF600 payable on site.

FURTHER INFORMATION

We will be sending out detailed invitations, programmes and registration
 instructions from your local Synopsys office in July.  In the meantime
 should you require further information please contact your local Synopsys
 applications engineering manager or the conference chair:

  Roderick Urquhart
  Synopsys European HQ,
  Stefan-George-Ring 24, D-81929  Munich, Germany
  Tel: +49 89 99 39 1233
  Fax: +49 89 99 39 1232

For information of EURO-DAC with EURO-VHDL 1994 please contact:

  MESAGO  Messe & Kongress GmbH
  Rotebuelstrasse 83-85, D-70178 Stuttgart, Germany
  Tel: +49 711 61046 0
  46ax: +49 711 618079

               -----------------------------------
               CALL FOR  PAPERS - SNUG Europe 1994
               -----------------------------------

AN INVITATION TO CONTRIBUTE

If you are interested in presenting your experiences with a contribution in
 a user session please forward a brief abstract or idea for your
 presentation to the conference chair SOON!.  You will be notified of
 the acceptance of your participation by 27th July and we will need your
 paper/presentation hard copy for publication in the SNUG binder by 7th
 September.

Several user presentations of about 20-30 minutes are sought in the following
 areas:

Design Methods and Flows

The theme of this session is Design Productivity.  Contributions are invited
 in the areas of design methodology and flow for both ASIC and system design
 projects.   Subjects of interest include system simulation, modelling
 strategies, ASIC prototyping using FPGAs, DSP design, design management,
 etc.

Tool Productivity

The theme of this session is Tool Productivity; focusing on gaining the most
 from particular Synopsys tools. Subjects of interest include HDL coding
 tricks, tips for simulation and synthesis performance, FPGA design,
 application of COSSAP, design for test, script automation, etc.

SEMICONDUCTOR PARTNER BREAKOUT

This session aims to cover design flow and integration issues when using
 Synopsys HLD tools to target implementation in silicon with a number of our
 semiconductor vendor partners.   Six invited 30 minute presentations will
 be scheduled in which our partners will have an opportunity to present
 their particular library support, links to layout and design flow
 integration to Synopsys.  User contributions in this session are welcomed
 via astute audience questioning and reaction to the presentations.

FURTHER INFORMATION

Should you wish to discuss your potential contribution, please feel free to
 contact your local applications engineering manager or Roderick Urquhart,
 the SNUG Europe '94 Conference Chair.

   Roderick Urquhart,
   Synopsys Europe,
   Stefan-George-Ring 24, D-81929  Munich,
   Germany.
   Tel: +49 89 99 39 12 33
   Fax: +49 89 99 39 12 32

===========================================================================
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     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Mon, 30 Dec 1996 16:03:09 GMT  
 
 [ 1 post ] 

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