Verilog Training Available 
Author Message
 Verilog Training Available

Hi,

I have a 2 day Introduction to Verilog class. At the end of this
2 day class the attendee will be able to

1. Learn Verilogs capabilities and place in the design flow
2. Write RTL and behavi{*filter*}Verilog models
3. Use various techniques for writing test benches
4. Understand Verilog simulation and debugging concepts
5. Predict how  synthesis tools interpret Verilog RTL
6. Develop Standard cell/ASIC libraries

The class will be thought on-site and I am also willing
 to consider customizing the class for specific needs.

If you are interested please contact me

Venkata Atluri
ASIC design and EDA flow consultant
Cupertino, CA 95014




Sun, 27 May 2001 03:00:00 GMT  
 
 [ 1 post ] 

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