verilog vs VHDL 
Author Message
 verilog vs VHDL

Paul, I am also reading the VHDL newsgroup, and I notice that they are quite
busy over there. I thought Verilog is much more popular . Hmmm


Fri, 17 Jan 2003 03:00:00 GMT  
 verilog vs VHDL

Quote:

> Paul, I am also reading the VHDL newsgroup, and I notice that they are quite
> busy over there. I thought Verilog is much more popular . Hmmm

With VHDL, you have much more trouble. So designers post much more
questions, compared to Verilog designers ;-))

Lars
--
Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL

Quote:


> > Paul, I am also reading the VHDL newsgroup, and I notice that they are quite
> > busy over there. I thought Verilog is much more popular . Hmmm

> With VHDL, you have much more trouble. So designers post much more
> questions, compared to Verilog designers ;-))

> Lars
> --
> Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
> Tel:      +(49) 621 181-2716, Fax: -2713

> Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/

Yes, I could not agree more.  I've coded in both.  The first that I had
experience with was VHDL and I used to think, wow, VHDL is way more
popular because the comp.lang.vhdl ng has way more activity.  Well, I
now seriously believe that it has more activity because the users
(especially the new ones) are so confused and have so many questions
regarding the language.  I'm not knocking VHDL, I'm using it once
again.  It's an excellent HDL, but it's got a steeper learning curve
than Verilog does.
--
Marty


Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL

Quote:
> Yes, I could not agree more.  I've coded in both.  The first that I had
> experience with was VHDL and I used to think, wow, VHDL is way more
> popular because the comp.lang.vhdl ng has way more activity.  Well, I
> now seriously believe that it has more activity because the users
> (especially the new ones) are so confused and have so many questions
> regarding the language.  I'm not knocking VHDL, I'm using it once
> again.  It's an excellent HDL, but it's got a steeper learning curve
> than Verilog does.
> --
> Marty

There must be an advatage using it over Verilog. That's why it's still being
used quite a bit in other parts of the world. Should a Verilog coder learn
VHDL ?


Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL
http://www1.fatbrain.com/interviews/sundar_rajan.html

Sundar: Sure. Okay, so the question was, "What do you think the strengths of
VHDL as compared to Verilog?"

Wow, loaded question. To be very frank with you, I think a lot of it boils
down to religion, you know, which is better MIPS instruction set or Intel?
And you find different people who have very strong opinions both ways. I've
used both and my feeling is that -- this is my opinion -- is that Verilog is
probably easier to learn initially, it is probably easier to get a design
done quickly, and it has some -- if you think about and use them carefully,
it has some nice features about it that lend themselves, you know, like lets
you take shortcuts.

Those are exactly the things that like VHDL is good, I think VHDL is
extremely good at structured, it does structure design I think far better
than Verilog. In other words, it allows you to do the sense of components
and entities and architecture and structuring, you know, when you're doing
top down or bottom up design, it really lends itself well to that kind of
structured disciplined design. It forces you to think about types, when you
assign a number to zero, it doesn't let you do that between different types,
if forces you to enforce a discipline. So it types match, and things like
that.

I also think VHDL is far better for algorithmic kinds of problems. If you're
doing state machines or if your design is very control intensive, I find
that. I think some of my biases are also probably because I'm much more
familiar with VHDL than the Verilog. So you should probably take that into
account in my response.



Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL

Quote:

> There must be an advantage using it over Verilog. That's why it's still being
> used quite a bit in other parts of the world. Should a Verilog coder learn
> VHDL ?

I'm sure I'll be corrected on this.  :-)

It's my impression that VHDL is used more in Europe while Verilog is
used more in the US.  

The reason as I've heard it, is that at the beginning VHDL was an open
standard while Verilog was controlled by Cadence through a company it
bought.  Europeans in general prefer using officially released
standards to proprietary and de facto standards, and so gravitated
to VHDL.
--



Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL
But Verilog is now an open standard as well, and for a while now, correct ?


Quote:


> > There must be an advantage using it over Verilog. That's why it's still
being
> > used quite a bit in other parts of the world. Should a Verilog coder
learn
> > VHDL ?

> I'm sure I'll be corrected on this.  :-)

> It's my impression that VHDL is used more in Europe while Verilog is
> used more in the US.

> The reason as I've heard it, is that at the beginning VHDL was an open
> standard while Verilog was controlled by Cadence through a company it
> bought.  Europeans in general prefer using officially released
> standards to proprietary and de facto standards, and so gravitated
> to VHDL.
> --




Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL

Quote:

> > Yes, I could not agree more.  I've coded in both.  The first that I had
> > experience with was VHDL and I used to think, wow, VHDL is way more
> > popular because the comp.lang.vhdl ng has way more activity.  Well, I
> > now seriously believe that it has more activity because the users
> > (especially the new ones) are so confused and have so many questions
> > regarding the language.  I'm not knocking VHDL, I'm using it once
> > again.  It's an excellent HDL, but it's got a steeper learning curve
> > than Verilog does.
> > --
> > Marty

> There must be an advatage using it over Verilog. That's why it's still being
> used quite a bit in other parts of the world. Should a Verilog coder learn
> VHDL ?

Yes.  I think at a minimum it makes you a more marketable logic
designer/verfication engineer to know both.  Then there is the mixed
mode simulators in which you can run your (for example) SDRAM controller
done in Verilog against some vendors SDRAM model done in VHDL (maybe a
bad example as most vendors have both VHDL and Verilog models of their
devices.  But hey, it is an example).  Then there are some things that
one HDL can do that the other cannot.  Basically, it doesn't hurt to
know both and by learning VHDL first, Verilog was pretty easy to pick up
(for me anyway).
--
Marty Pietruszka

http://www.geocities.com/m_piet


Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL

True.  But by the time it opended up VHDL attained a following.

Quote:

> But Verilog is now an open standard as well, and for a while now, correct ?


> > It's my impression that VHDL is used more in Europe while Verilog is
> > used more in the US.

> > The reason as I've heard it, is that at the beginning VHDL was an open
> > standard while Verilog was controlled by Cadence through a company it
> > bought.  Europeans in general prefer using officially released
> > standards to proprietary and de facto standards, and so gravitated
> > to VHDL.

--



Sat, 18 Jan 2003 03:00:00 GMT  
 verilog vs VHDL
Quote:

> http://www1.fatbrain.com/interviews/sundar_rajan.html

> Sundar: Sure. Okay, so the question was, "What do you think the strengths of
> VHDL as compared to Verilog?"

> Wow, loaded question. To be very frank with you, I think a lot of it boils
> down to religion, you know, which is better MIPS instruction set or Intel?
> And you find different people who have very strong opinions both ways. I've
> used both and my feeling is that -- this is my opinion -- is that Verilog is
> probably easier to learn initially, it is probably easier to get a design
> done quickly, and it has some -- if you think about and use them carefully,
> it has some nice features about it that lend themselves, you know, like lets
> you take shortcuts.

.....

Religon aside, there are some fundamental differences between Verilog &
VHDL:

1. Bidirectional devices

   Verilog supports bidirectional signal flow in primitives, VHDL does
   not support it at all.

   => You can't do transistor-level (CMOS) stuff easily in VHDL.

2. Signal Resolution

   Resolution in Verilog is flat, and in VHDL is hierarchical. VHDL
   additionally allows port-bound signal conversion.

   => Signals in VHDL do not (in general) behave the same as physical
   wires.

3. User defined types

   Not supported in Verlog.

My opinion is that VHDL is Good/OK as an abstract simulation language (which
you can use with Synthesis etc.) but near useless as a hardware (implementation)
verification tool. So if you need to do the latter, you may want to stick with
Verilog throught your design flow.

Items 1 & 2 above become more of a problem with VHDL-AMS.

Kev.



Sun, 26 Jan 2003 03:00:00 GMT  
 verilog vs VHDL
On Wed, 09 Aug 2000 11:07:20 -0700, Kevin Cameron x3251

Quote:

>Religon aside, there are some fundamental differences between Verilog &
>VHDL:

>1. Bidirectional devices

>   Verilog supports bidirectional signal flow in primitives, VHDL does
>   not support it at all.

>   => You can't do transistor-level (CMOS) stuff easily in VHDL.

>2. Signal Resolution

>   Resolution in Verilog is flat, and in VHDL is hierarchical. VHDL
>   additionally allows port-bound signal conversion.

>   => Signals in VHDL do not (in general) behave the same as physical
>   wires.

>3. User defined types

>   Not supported in Verlog.

>My opinion is that VHDL is Good/OK as an abstract simulation language (which
>you can use with Synthesis etc.) but near useless as a hardware (implementation)
>verification tool. So if you need to do the latter, you may want to stick with
>Verilog throught your design flow.

>Items 1 & 2 above become more of a problem with VHDL-AMS.

>Kev.

There are some fundamental differences, and some surprising
similarities. If you don't mind me saying so, your list above doesn't
do justice to either. Point (1) is relevant only to a (very) small
number of users, and point (2), as far as I can see, has no practical
significance. I don't want to get involved in a VHDL/Verilog flame,
and I want to do this in 10 minutes, rather than several hours, but
you should also consider, among many other things:

1)      Scheduling is fundamentally different. The practical effect of
this is that Verilog sims should be faster, but can suffer from
non-determinism.

2)      Structural hierarchy is a lot more flexible in VHDL, via the
use of entity/architecture pairs, and configurations. It's easier to
manage designs using packages and libraries.

3)      There is no fundamental difference in what can be synthesised
between the 2 languages, contrary to frequent statements here. Many of
the useful extra syntax features of VHDL (see (11)) are also
synthesisable. Both VHDL and Verilog have synthesis subsets.

4)      VHDL is much more strongly typed than Verilog; scope is
rigourously defined; you have to declare just about everything before
you use it; and so on. Some argue that this is a bad thing; others
that it's essential. VHDL's types are also extensible, through
enumerated types. This is both useful and synthesisable.

5)      VHDL is more verbose than Verilog. Sometimes there's a good
reason for this (see (2) and (4) above); sometimes there isn't.
Whether this is a significant problem is debatable.

6)      VHDL's and Verilog's antecedents are Ada and C, respectively.
This makes some of Verilog familiar to most engineers. However,
contrary to popular belief, there is very little direct similarity
between Verilog and C.

7)      VHDL doesn't have system tasks or compiler directives. The
system tasks have to be implemented through explicit coding, use of
libraries, or through a PLI. Compiler directives require an external
preprocessor.

8)      VHDL doesn't have a standard PLI. Sim vendors have their own
PLIs.

9)      VHDL doesn't make a distinction between nets and registers; it
has signals instead. The confusion between blocking  and non-blocking
assignments is avoided for a number of reasons, including tighter
scoping, and more rigorous scheduling.

10)     It's easier to parameterise VHDL designs.

11)     VHDL has a richer syntax; examples that come to mind are
generates, conditional and selected signal assignments,
multi-dimensional arrays, more usable functions and procedures/tasks,
easier initialisation, ANSI-C style declarations, attributes,
enumerated types. These are all synthesisable.

12)     VHDL has nothing equivalent to a fork-join, or block
disabling.

13)     Some ASIC vendors may not let you use VHDL. This is a
significant problem for VHDL, but can generally be got around, if only
by generating Verilog gate-level netlists.

14)     Verilog 2000 will fix some of the more obvious syntax
omissions. There is also an updated VHDL on the way, but it won't be
soon.

15)     You should be able to produce a simple design quicker if
you're learning Verilog. However, the total area under the learning
curve is much the same for both languages.  

16)     In short, VHDL is much more rigorous as a computer language,
is better defined, and provides a more complete single-language
simulation and synthesis solution. The price you pay is more
verbosity, a steeper learning curve, possibly slower simulation, and
possible marginalisation in some parts of the world. You're more
likely to get a job in Europe with VHDL, and in the US with Verilog.

Evan



Sun, 26 Jan 2003 03:00:00 GMT  
 
 [ 11 post ] 

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