$setuphold and Verilint 
Author Message
 $setuphold and Verilint

Hello world,

According to the LRM (pg 189, section 14.5.3) $setuphold
has the following syntax:

$setuphold (reference_event, data_event, setup_limit, hold_limit, [ notifier]);

I have extracted this line from a vendor's library:

$setuphold(posedge CP, posedge D, 0.0469:0.0469:0.0469, -0.0234:-0.0234:-0.0234,
notifier1, , DCD, DCP, DD);

Note the 4 fields after the notifier...

But the question is, why is Verilint complaining?

(E363)    CELL.v, line  42: Syntax error:  DCD, DCP, DD);

Obviously because of the whitespace (, ,)...

Anyone have a workaround for this?

Thanks,
/Ed
--



Mon, 11 Feb 2002 03:00:00 GMT  
 $setuphold and Verilint
Verilint is complaining about the new syntax of $setuphold which was
developed (by ASIC Taskforce?) to effectively implement the -ve setup/hold
constraints.

In this syntax, the D input of the real sequential element is delayed
through the specification of incoming fanin D input and fanout D output in
the $setuphold task.

This is a recent addition and may not have been implemented by verilint.

I do not think it is part of standard as yet, but many simulators have
already implemented it under pressure from ASIC vendors.

-Ashutosh


Quote:
> Hello world,

> According to the LRM (pg 189, section 14.5.3) $setuphold
> has the following syntax:

> $setuphold (reference_event, data_event, setup_limit, hold_limit,
 notifier]);

> I have extracted this line from a vendor's library:

> $setuphold(posedge CP, posedge D,

0.0469:0.0469:0.0469, -0.0234:-0.0234:-0.0234,
Quote:
> notifier1, , DCD, DCP, DD);

> Note the 4 fields after the notifier...

> But the question is, why is Verilint complaining?

> (E363)    CELL.v, line  42: Syntax error:  DCD, DCP, DD);

> Obviously because of the whitespace (, ,)...

> Anyone have a workaround for this?

> Thanks,
> /Ed
> --




Mon, 11 Feb 2002 03:00:00 GMT  
 $setuphold and Verilint
Hello,

I am looking for tools for doing automated conversion
from synthesizable Verilog RTL code to C (or C++).

This would be useful for generating an executing model
of hardware for software development purposes.

I am investigating CAE Plus and Cynapps, but if there
are any others I should know about, I would appreciate
any help.

Tom Loftus
Hughes Network Systems



Tue, 12 Feb 2002 03:00:00 GMT  
 $setuphold and Verilint
Hello,

I am looking for tools for doing automated conversion
from synthesizable Verilog RTL code to C (or C++).

This would be useful for generating an executing model
of hardware for software development purposes.

I am investigating CAE Plus and Cynapps, but if there
are any others I should know about, I would appreciate
any help.

Tom Loftus
Hughes Network Systems



Tue, 12 Feb 2002 03:00:00 GMT  
 $setuphold and Verilint
Hello,

I am looking for tools for doing automated conversion
from synthesizable Verilog RTL code to C (or C++).

This would be useful for generating an executing model
of hardware for software development purposes.

I am investigating CAE Plus and Cynapps, but if there
are any others I should know about, I would appreciate
any help.

Tom Loftus
Hughes Network Systems

Sorry for the multiple postings.



Tue, 12 Feb 2002 03:00:00 GMT  
 $setuphold and Verilint

Quote:

> Hello,

> I am looking for tools for doing automated conversion
> from synthesizable Verilog RTL code to C (or C++).

> This would be useful for generating an executing model
> of hardware for software development purposes.

> I am investigating CAE Plus and Cynapps, but if there
> are any others I should know about, I would appreciate
> any help.

> Tom Loftus
> Hughes Network Systems

> Sorry for the multiple postings.

Hi Tom,
        Check out Escalade's IPGuard (http://www.escalade.com)
The current version converts Verilog to C and in future
they are planing to do the same for VHDL as well (that's
what is more interesting to me)

Regards,
Srini



Fri, 15 Feb 2002 03:00:00 GMT  
 $setuphold and Verilint


Quote:

> > Hello,

> > I am looking for tools for doing automated conversion
> > from synthesizable Verilog RTL code to C (or C++).

> > This would be useful for generating an executing model
> > of hardware for software development purposes.

> > I am investigating CAE Plus and Cynapps, but if there
> > are any others I should know about, I would appreciate
> > any help.

> > Tom Loftus
> > Hughes Network Systems

> > Sorry for the multiple postings.

> Hi Tom,
>    Check out Escalade's IPGuard (http://www.escalade.com)
> The current version converts Verilog to C and in future
> they are planing to do the same for VHDL as well (that's
> what is more interesting to me)

> Regards,
> Srini

If VHDL2c is required, there is adecent translator at
http://www.co.umist.ac.uk/~xtian/v2c/v2c.html.

Though I didn't evaluate it thoroughly, it did a good job
for most of RTL constricts in VHDL. Above all it's free.
If you fined some bugs one can up-date the c code.

-Murali.

Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.



Sun, 17 Feb 2002 03:00:00 GMT  
 $setuphold and Verilint
Hi,

We at CAE+plus have launched a new product by the name AfterBurner,
exclusively for converting Verilog to RTL-C. Your query has been
forwarded to our parent co. in the U.S. They should get back to you
soon.

regards

Sameer Goel
********************************************************************
VLSI Software Pvt. Ltd.
( a subsidiary of CAE-Plus Inc., USA)
C-97 ,  Sector 2
NOIDA  201301
INDIA
Phones : +91-11-91-531144, 555277. 550125

visit us at www.cae-plus.com
*********************************************************************



Quote:
> Hello,

> I am looking for tools for doing automated conversion
> from synthesizable Verilog RTL code to C (or C++).

> This would be useful for generating an executing model
> of hardware for software development purposes.

> I am investigating CAE Plus and Cynapps, but if there
> are any others I should know about, I would appreciate
> any help.

> Tom Loftus
> Hughes Network Systems

> Sorry for the multiple postings.

Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.


Wed, 27 Feb 2002 03:00:00 GMT  
 
 [ 9 post ] 

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