HP Spokane R&D ASIC Project Manager 
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 HP Spokane R&D ASIC Project Manager

          Please do not contact the poster of this message.

                     R&D ASIC Project Manager

            --  Principles only (no agencies) please. --

     Please respond with your cover letter and resume (E-mail preferred) to:

     Ron Brazee
     Hewlett-Packard Spokane Division M/S 3WU
     24001 East Mission Ave.
     Liberty Lake, WA.  99019

     509-921-4345

     ________________________________________________________________
     Job Title:             R&D Project Manager
     Department:            Research & Development
     Division:              Spokane
     City:                  Spokane
     State:                 Washington

     JOB FUNCTIONS:
     Essential: (Major Responsibilities)

     Manage team of Design Engineers assigned the responsibility of
     providing ASIC and high speed digital designs in Communications Test
     Equipment.  

     Actively work with R&D Lab Engineers, Project Managers, and
     Section Managers to develop and execute a long term
     Product/Productivity strategy for both ASICs (Digital, Analog,
     and mixed mode) and Digital PC board designs and design
     capabilities (both for the group itself and the part-time digital
     designers elsewhere in R&D).

     Other Duties: (Marginal Responsibilities)

     Develop and implement the test and support strategies for ASICS,
     and manage strategic CAE and foundry relationships.

    SKILLS/KNOWLEDGE QUALIFICATIONS:

    MUSTS - Minimum Degree/Experience

     *Bachelor's degree or equivalent in Electrical Engineering, Computer
      Science or related scientific disciplines.

     *Minimum of three years of related (ASIC or high speed digital
      design) design experience, including working familiarity with
      requirements capture, behavi{*filter*}(HDL) modeling, simulation,
      design rule checks, synthesis, design for test, foundry
      submission and sign off, semiconductor technology lifecycles,
      and PC Board lifecycles.

     *Demonstrated ability to manage/lead a group of technical
      contributors, building the necessary skills and teamwork.

     *Demonstrated ability to manage/lead a technical project
      successfully, including the ability to build and maintain
      effective working relationships across organizational &
      divisional boundaries.

     *Proven ability to exercise independent judgment.

    DESIRED - Preferred Degree/Experience

     *Masters Degree in Engineering or Computer Science preferred.

     *Previous management/supervisory experience

     *Familiarity with a subset of the following tools, device
      processes, and standards: Synopsys, Mentor, Cadence, HPEEsof,
      VHDL, event driven and cycle based simulation, floorplanning,
      test insertion and ATPG, hardware modeling, ASIC emulation,
      Spice, harmonic balance, high frequency structure simulation.

     *Familiarity with broad range of ASIC technologies (CMOS, BiCMOS,
      Bipolar, GaAs, and multi-chip modules) and digital board
      families (VME, PCI, x86, 680xx), as well as digital signal
      integrity and EMI design and analysis techniques.

     *Previous experience coordinating applicable technology
      improvements across Functional (and/or Divisional) boundaries
      (e.g., use of HW/SW co-simulation to reduce integration effort,
      simulation to reduce board or chip turns, etc.).

     *General RF Communications Test knowledge, including measurement
      algorithms & techniques.

     _________________________________________________________________



Tue, 23 May 2000 03:00:00 GMT  
 
 [ 1 post ] 

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