New EMACS mode for VHDL/Verilog 
Author Message
 New EMACS mode for VHDL/Verilog

Not being satisfied with the EMACS modes currently available for VHDL
and not finding a Verilog mode that worked under EMACS 19, I decided
to write my very own minimalist VHDL/Verilog mode.

Personnaly, I *hate* being prompted for a lot of stuff and I'm
familiar enough with the syntax that I don't need templates being
filled in for me. All this mode does is (what I think is) proper
indentation and dynamic abbreviation expansion (I shamelessly stole
the dabbrev idea from Honeywell's VHDL mode (Hi Todd!)).

Since most of the stuff is the same between Verilog and VHDL, I merged
both modes in a single HDL package (although they still are separate
modes).

It is still very new and can use some improvement. Suggestions and
bug fixes welcome. See the header comment for usage instructions.

Anybody knows how to bind "shift-tab" ?

--
Janick Bergeron           AnalySYS Inc.                  Ph.: (613) 443-0428
System Verification   25 Loiselle St, Suite 201          Fax: (613) 443-0428

          VHDL  -  Verilog  -  Synthesis  -  QuickTurn Emulation

;;
;; Minimal VHDL/Verilog mode for EMACS
;;
;; Distributed under the terms of the GNU copyleft.
;; (c) Copyrights AnalySYS Inc., 1995
;;     All rights reserved.
;;
;; Janick Bergeron, HDL Consultant
;; AnalySYS Inc.
;; 25 Loiselle St, Suite 201
;; Embrun, ON, Canada, K0A 1W1

;;
;; Version number: 1.0a
;; Last Updated: Tue Jan 24 16:13:43 1995
;;
;; Suggestions/bug fixes welcome
;;
;;
;; If you hit TAB:
;; - In the left margin or beginning
;;   of the line                        The line is indented with previous line
;; - At the start of the line           The line is indented one extra level
;; - In the middle of a line            A TAB is inserted
;;
;; If you hit M-TAB:
;; - In the left margin                 The line is undented by 1 level
;; - At the right of an identifier      Symbol on left is expanded
;;
;; Use ^Ch to insert a standard header at the top of the file
;; Use ^Cb to beautify the content of the buffer
;;
;;
;; Revision History:
;;
;; 1.0
;;   a   Initial public release
;;

(require 'dabbrev)

;;
;; User options
;;

(setq auto-mode-alist (cons (cons "\\.vhd$" 'vhdl-mode) auto-mode-alist))
(setq auto-mode-alist (cons (cons "\\.v$" 'verilog-mode) auto-mode-alist))

(defvar vhdl-header-file-name "~/vhdl/header.vhd"
 "*Name of the file containing the standard VHDL file header")
(defvar verilog-header-file-name "~/verilog/header.v"
 "*Name of the file containing the standard verilog file header")

(defvar vhdl-beautifier "~/vhdl/beautifier"
 "*Name of the VHDL beautifier program or nil if not available")
(defvar verilog-beautifier "~/verilog/reCapitalize"
 "*Name of the Verilog beautifier program or nil if not available")

(defvar hdl-indent 4
 "*Value is the number of columns to indent in HDL-Mode.")

;;
;; VHDL
;;

(defvar vhdl-mode-syntax-table nil
  "Syntax table in use in vhdl-mode buffers.")

(let ((table (make-syntax-table)))
  (modify-syntax-entry ?_ "w" table)
  (modify-syntax-entry ?\# "w" table)
  (modify-syntax-entry ?\( "()" table)
  (modify-syntax-entry ?\) ")(" table)
  (modify-syntax-entry ?* "." table)
  (modify-syntax-entry ?/ "." table)
  (modify-syntax-entry ?+ "." table)
  (modify-syntax-entry ?- "< 12" table)
  (modify-syntax-entry ?\n ">" table)
  (modify-syntax-entry ?= "." table)
  (modify-syntax-entry ?\& "." table)
  (modify-syntax-entry ?< "." table)
  (modify-syntax-entry ?> "." table)
  (modify-syntax-entry ?. "." table)
  (modify-syntax-entry ?\\ "\"" table)
  (modify-syntax-entry ?: "." table)
  (modify-syntax-entry ?\; "." table)
  (modify-syntax-entry ?\' "." table)
  (modify-syntax-entry ?\" "\"" table)
  (setq vhdl-mode-syntax-table table))

(defvar vhdl-mode-map nil
  "Keymap used in VHDL mode.")

(let ((map (make-sparse-keymap)))
  (define-key map "\C-m" 'hdl-newline)
  (define-key map "\C-i" 'hdl-tab)
  (define-key map "\M-\C-i" 'hdl-untab)
  (define-key map "\C-cb" 'vhdl-beautify)
  (define-key map "\C-ch" 'vhdl-header)
  (setq vhdl-mode-map map))

(defun vhdl-mode ()
"This is a mode intended to support program development in VHDL.
Variable `hdl-indent' controls the number of spaces for indent/undent."
  (interactive)
  (kill-all-local-variables)
  (use-local-map vhdl-mode-map)
  (setq major-mode 'vhdl-mode)
  (setq mode-name "VHDL")
  (set-syntax-table vhdl-mode-syntax-table)
  (make-local-variable 'require-final-newline)
  (setq require-final-newline t)
  (make-local-variable 'indent-tabs-mode)
  (setq indent-tabs-mode nil)
  (run-hooks 'vhdl-mode-hook))

(defun vhdl-header ()
  "Insert a comment block containing the module title, author, etc."
  (interactive)
  (hdl-header vhdl-header-file-name))

(defun vhdl-beautify ()
  "Beautify the VHDL source code in the buffer"
  (interactive)
  (hdl-beautify vhdl-beautifier))

;;
;; Verilog
;;

(defvar verilog-mode-syntax-table nil
  "Syntax table in use in verilog-mode buffers.")

(let ((table (make-syntax-table)))
  (modify-syntax-entry ?_ "w" table)
  (modify-syntax-entry ?\# "." table)
  (modify-syntax-entry ?\( "()" table)
  (modify-syntax-entry ?\) ")(" table)
  (modify-syntax-entry ?\[ "(]" table)
  (modify-syntax-entry ?\] ")[" table)
  (modify-syntax-entry ?\{ "(}" table)
  (modify-syntax-entry ?\} "){" table)
  (modify-syntax-entry ?^ "." table)
  (modify-syntax-entry ?| "." table)
  (modify-syntax-entry ?* ". 23" table)
  (modify-syntax-entry ?/ "< 124b" table)
  (modify-syntax-entry ?+ "." table)
  (modify-syntax-entry ?- "." table)
  (modify-syntax-entry ?\n "> b" table)
  (modify-syntax-entry ?= "." table)
  (modify-syntax-entry ?\& "." table)
  (modify-syntax-entry ?< "." table)
  (modify-syntax-entry ?> "." table)
  (modify-syntax-entry ?. "." table)
  (modify-syntax-entry ?\? "." table)
  (modify-syntax-entry ?: "." table)
  (modify-syntax-entry ?\; "." table)
  (modify-syntax-entry ?\' "." table)
  (modify-syntax-entry ?\` "." table)
  (modify-syntax-entry ?\" "\"" table)
  (setq verilog-mode-syntax-table table))

(defvar verilog-mode-map nil
  "Keymap used in Verilog mode.")

(let ((map (make-sparse-keymap)))
  (define-key map "\C-m" 'hdl-newline)
  (define-key map "\C-i" 'hdl-tab)
  (define-key map "\M-\C-i" 'hdl-untab)
  (define-key map "\C-cb" 'verilog-beautify)
  (define-key map "\C-ch" 'verilog-header)
  (setq verilog-mode-map map))

(defun verilog-mode ()
"This is a mode intended to support program development in Verilog.
Variable `hdl-indent' controls the number of spaces for indent/undent."
  (interactive)
  (kill-all-local-variables)
  (use-local-map verilog-mode-map)
  (setq major-mode 'verilog-mode)
  (setq mode-name "Verilog")
  (set-syntax-table verilog-mode-syntax-table)
  (make-local-variable 'require-final-newline)
  (setq require-final-newline t)
  (make-local-variable 'indent-tabs-mode)
  (setq indent-tabs-mode nil)
  (run-hooks 'verilog-mode-hook))

(defun verilog-header ()
  "Insert a comment block containing the module title, author, etc."
  (interactive)
  (hdl-header verilog-header-file-name))

(defun verilog-beautify ()
  "Beautify the Verilog source code in the buffer"
  (interactive)
  (hdl-beautify verilog-beautifier))

;;
;; Generic to HDLs
;;

(defun hdl-tabsize (s)
  "Changes spacing used for indentation.
The prefix argument is used as the new spacing."
  (interactive "p")
  (setq hdl-indent s))

(defun hdl-newline ()
  "Start new line and indent to current tab stop."
  (interactive)
  (newline)
  (hdl-tab))

(defun hdl-tab ()
  "Indent to next tab stop."
  (interactive)
  (save-excursion
    (beginning-of-line)
    (looking-at "[ \t]*"))
  (if (< (match-end 0) (point))
      (insert "\t")
    (if (and (not (bolp)) (= (match-end 0) (point)))
        (indent-to (+ (current-indentation) hdl-indent))
      (let ((tmp (parse-partial-sexp (point-min) (point)))
            hdl-cc last-start here)
        (setq hdl-cc (car (cdr tmp)))
        (setq last-start (car (cdr (cdr tmp))))
        (save-excursion
          (if hdl-cc
              (progn
                (goto-char hdl-cc)
                (setq hdl-cc (1+ (current-column))))
            (forward-line -1)
            (setq here (point))
            (setq hdl-cc (current-indentation))
            (if (not last-start)
                nil
              (goto-char last-start)
              (setq last-start (current-indentation))
              (forward-sexp 1)
              (if (> (point) here)
                  (setq hdl-cc last-start)))))
        (replace-match "")
        (indent-to hdl-cc)))))

(defun hdl-untab ()
  "Un-indent to previous tab stop."
  (interactive)
  (save-excursion
    (beginning-of-line)
    (looking-at "[ \t]*"))
  (if (< (match-end 0) (point))
      (if (and (= (char-syntax (preceding-char)) ?w)
               (not (= (char-syntax (following-char)) ?w)))
          (let ((case-fold-search t)) (dabbrev-expand 1)))
    (let ((cur-indent (current-indentation)))
      (replace-match "")
      (indent-to (* (1- (/ cur-indent hdl-indent)) hdl-indent)))))

(defun hdl-header (file-name)
  "Insert a comment block containing the module title, author, etc."
  (interactive)
  (goto-char (point-min))
  (insert-file (expand-file-name file-name)))

(defun hdl-beautify (program-name)
  "Beautify the source code in the buffer"
  (interactive)
  (if program-name
      (call-process-region (point-min) (point-max) (expand-file-name program-name) t t t)))

;;
;; Error message formats
;;

(require 'compile)

;;Verilog-XL error format:
;;Error!    syntax error                                      [Verilog]
;;          "XS800_CELL.v", 125: if (WORD[i] !== 16'h0000)
(setq compilation-error-regexp-alist
      (append '(("] *\n          \"\\([^\"]+\\)\", \\([0-9]+\\):" 1 2))
                    compilation-error-regexp-alist))

;; Verilint error format:
;;(E363)  harness.v 119: Syntax error :    .TDO(
(setq compilation-error-regexp-alist
      (append '(("\([EW][0-9]+\) *\\([^ \t]+\\) *\\([0-9]+\\):" 1 2))
                    compilation-error-regexp-alist))



Sun, 13 Jul 1997 05:29:10 GMT  
 New EMACS mode for VHDL/Verilog
.
[misc stuff deleted]
.
|> Anybody knows how to bind "shift-tab" ?

(global-set-key [S-tab] 'indent-relative)

--
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--------------------------------------------------------------------



Sun, 13 Jul 1997 20:10:13 GMT  
 New EMACS mode for VHDL/Verilog

JB> Not being satisfied with the EMACS modes currently available for VHDL
I haven't been either...  :)

JB> indentation and dynamic abbreviation expansion (I shamelessly stole
JB> the dabbrev idea from Honeywell's VHDL mode (Hi Todd!)).
Hi, Janick!  Actually, I was running with pretty much the same thing here.
Mainly 'cuz our old mode was toast under v19 (the old dabbrev bugs that we
patched were replaced with new ones...)  Except, I'm using the wonderfully
excellent vhdl-mode indentation engine from Rod Whitby.  On top of it I put
our comments and dabbrev as an electrified mode.  I'm also working on a
template mode that is less intrusive than the old mode (it fires off of
M-TAB, since I couldn't figure out shift tab either...).  However, I'm much
less than impressed with the particular template mode that comes with
v19.25, so all that might be ripped back out.

Anyways, I'm willing to send out the latest I have, to those willing.
Everything else seems solid, the template are still in flux.  Rod himself
is currently unable to distribute his indenting mode, but I have leave from
him to distribute the last version he sent me.

Send me email...

And true to form, this mode *is* VHDL centric.  :) :) :)

Todd P. Carpenter                                
Honeywell Technology Center 3660 Technology Drive, MPLS MN 55418-1006

User Man, p34 l5: Opinion possesion unauthorized for this carbon unit



Sun, 13 Jul 1997 15:25:11 GMT  
 
 [ 3 post ] 

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