SystemC 
Author Message
 SystemC

Hi.

Just a few questions about SystemC - very grateful for all answers...

    Are SystemC hardware models synthesizeable?
    Would the OO nature of SystemC aid hardware re-use?
    Would running a hardware/software co-simulation in SystemC be
significantly faster/slower than in an RTL simulator?

Thanks in advance,

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Brendan Lynskey
Comodo Research Lab

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Sun, 16 Oct 2005 19:33:09 GMT  
 SystemC
Hi Brendan,

Quote:
> Just a few questions about SystemC - very grateful for all answers...

>     Are SystemC hardware models synthesizeable?

It's the same story as in VHDL: Some will be and some won't
be synthesizable.

Btw., Synopsys has developed some synthesizer for SystemC right now.
But I can't tell you how advanced it is at the moment.

Quote:
>     Would the OO nature of SystemC aid hardware re-use?

I think the reusability is independent from object orientation.
It's actually the same as in common programming languages.
You don't need an object oriented language (say C++) in order
to reuse functions. The same thing can be achieved in a common
language (say C).

The reason main why SystemC is based on C++ rather than C is
that there you have a chance to overload operators. Generally,
SystemC is not heavily object oriented. This is also explicitely
stated somewhere (i.e. you do not need extensive C++ skills in
order to make use of SystemC).

Quote:
>     Would running a hardware/software co-simulation in SystemC be
> significantly faster/slower than in an RTL simulator?

I can't tell you that as I have made no experiments yet.
But you can make a try by yourself. The simulator core for
SystemC is free - even Open Source!

Regards,
Mario

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Mon, 17 Oct 2005 17:08:19 GMT  
 SystemC

Quote:
> Hi.

> Just a few questions about SystemC - very grateful for all
answers...

>     Are SystemC hardware models synthesizeable?

Yes, if written in a synthesisable subset of SystemC. There
are
tools from Synopsys, Forte Design Systems, and Future Design
Automation
(and possibly others I've forgotten - see www.systemc.org
and click on
"products and solutions").

Quote:
>     Would the OO nature of SystemC aid hardware re-use?

Not necessarily, as another poster said SystemC is a C++
class library
which allows all the features of C++ such as operator
overloading to
be used. The main current use of SystemC seems to be in
platform Transaction
Level Modelling (platform TLM) rather than at RTL. At the
more abstract level
then you can achieve high levels of re-use. One of the main
aims of SystemC
is to promote re-use of testbenches at different levels of
abstraction.

Quote:
>     Would running a hardware/software co-simulation in
SystemC be
> significantly faster/slower than in an RTL simulator?

This is one of those "apples and oranges" questions! For
platform TLM, SystemC
can achieve something like 100x-1000x speed up over RTL
co-simulation essentially
by using an accurate bus model with simplified (abstract)
peripherals.

I don't have any figures comparing RTL in say Verilog vs
SystemC, but I would
expect SystemC to be slower with the reference simulator
from www.systemc.org,
simply because the kernel has not been developed and
improved for 20 years! Some
companies are implementing improved versions of the kernel
which run faster
(e.g. Coware)

regards

Alan

Quote:
> Thanks in advance,

> --
> Brendan Lynskey
> Comodo Research Lab

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Tue, 18 Oct 2005 16:17:22 GMT  
 
 [ 3 post ] 

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