Short Courses in Verilog HDL in Silicon Valley in March and April(Repost) 
Author Message
 Short Courses in Verilog HDL in Silicon Valley in March and April(Repost)

DATES :  March 20 (Wednesday) April 4 (Thursday) April 17(Wednesday)

LOCATION : PerformanCAE Corpration, 19925 Stevens Creek Blvd, Cupertino,

CA 95014

CONTENTS

     Verilog HDL Motivation
     Structural, RTL and Behavi{*filter*}Descriptions with Verilog
     Synthesis with Verilog
     IEEE 1364 standard
     Introduction to Advanced Verilog features
          Programming Language Interface
          Switch Level Simulation
          Specify Blocks - Timing Specifications
     Recent Developments in Verilog World
          Verilog-A and Verilog-MS; Analog and Mixed Signal Verilog
Language
          Behavi{*filter*}Synthesis
          Formal Verification
          Cycle Simulation
     Successful Verilog Design Cycle

   VHDL and Verilog - what they really are and
    where we are headed

FEES : $225.00 for full-day course

ENROLLMENT IS LIMITED


Thanks,
Vivek Sagdeo



Sun, 30 Aug 1998 03:00:00 GMT  
 
 [ 1 post ] 

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