12th ACM/IEEE International Conference on Computer-Aided Design 
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 12th ACM/IEEE International Conference on Computer-Aided Design

                       Advance Information

     12th ACM/IEEE International Conference on Computer-Aided Design

              November 6-10, 1994     San Jose, CA

           Preregistration deadline: October 14, 1994

   Contents of this post:
        1) conference sessions (with paper titles)
        2) registration form (print, clip, and mail)
        3) hotel reservation form (print, clip, and mail)


The  Twelth  International Conference on  Computer-Aided  Design,
ICCAD-94, will be held Nov. 6-10, 1994 at the Red Lion  Hotel  in
San Jose, California (a new venue that is much closer to San Jose
International Airport and is a better match to the style and size
of  this  meeting).   The  conference  concentrates  on  CAD  for
microelectronic  system  design  and  features  three   days   of
technical  sessions  organized  into  four  parallel  tracks   (a
successful change initiated last year), one day of four  full-day
tutorials,  a lively evening panel discussion, a final  panel  to
close  the  conference, and an informal buffet dinner  and  party
Tuesday  evening.   A  new  addition are  embedded  tutorials  on
Tuesday  afternoon on two topics becoming ever more  critical  to
the ICCAD community.

ICCAD-94  offers an exceptionally strong schedule of  papers  and
tutorials  composed by a committee of 80 referees.   The  program
promises   to  challenge  experienced  CAD  developers,  hardware
designers,  and academic researchers who want to learn  from  the
latest in CAD research and development.  As usual, there will  be
CAD  vendor  suites  to  offer conference  attendees  the  unique
opportunity  for in-depth technical discussions with  vendors  on
their latest products.

                       Technical Sessions

The  heart of the conference, the technical sessions, include 120
papers  representing  the best of over 462  submissions  (another
record  number).  The presentations represent the latest  in  CAD
work   from   industry,  research  laboratories,   and   academic
institutions.   Titles of the papers and their organization  into
sessions is provided below.  The reader is encouraged to  consult
the  Advance Program for a complete conference agenda,  schedule,
and  authors.  Copies of the Advance Program can be  obtained  by
contacting  the conference management, MP Associates, via  phone,
fax, or electronic mail as described below.


                 Sessions for Monday 7 November

Multi-Level Logic Optimization
        Perturb and Simplify: Multi-Level Boolean Network Optimizer
        Multi-Level Logic Optimization by Implication Analysis
        Incremental Synthesis

Memory Issues in High-Level Synthesis
        Definition And Solution Of The Memory Packing Problem
                for Field-Programmable Systems
        Integrating Program Transformations
                in the Memory-Based Synthesis of Image and Video Algorithms
        Dataflow-Driven Memory Allocation
                for Multi-Dimensional Signal Processing Systems

Test Generation
        Test Generation for Bridging Faults in Cmos ICs
                Based on Current Monitoring vs. Signal Propagation
        Iterative [Simulation Based Genetics + Deterministic Techniques]
                =  Complete ATPG
        Analytical Fault Modeling and Static Test Generation for Analog ICs

        Efficient Network Flow Based Min-Cut Balanced Partitioning
        Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation
        A General Framework for Vertex Orderings
                with Applications to Netlist Clustering

Sequential Synthesis for Low Power
        Re-Encoding Sequential Circuits to Reduce Power Dissipation
        Precomputation-Based Sequential Logic Optimization for Low Power
        Low Power State Assignment
                Targeting Two- and Multi-Level Logic Implementations

System Optimization, Partitioning, and Integration
        Algorithm Selection:
                A Quantitive Computation-Intensive Optimization Approach
        Adaptation of Partitioning and High-Level Synthesis
                in Hardware/Software Co-Synthesis
        Synthesis of Concurrent System Interface Modules
                with Automatic Protocol Conversion Generation

Built-In Self-Test
        An Efficient Procedure for the Synthesis of Fast Self-Testable
                Controller Structures
        Test Pattern Generation Based on Arithmetic Operations
        Random Pattern Testable Logic Synthesis

        Compression-Relaxation: A New Approach to Performance Driven Placement
                for Regular Architectures
        A Loosely Coupled Parallel Algorithm for Standard Cell Placement
        Delay and Area Optimization for Compact Placement
                by Gate Resizing and Relocation

FPGA Synthesis and Architecture
        Edge-Map: Optimal Performance Driven Technology Mapping
                for Iterative LUT-Based FPGA Designs
        Maple: A Simultaneous Technology Mapping, Placement,
                and Global Routing Algorithm for FPGAs
        Universal Logic Gate for FPGA Design

Concurrency Modeling and Estimation
        Condition Graphs for High-Quality Behavi{*filter*}Synthesis
        Dynamic Scheduling and Synchronization Synthesis
                of Concurrent Digital Systems under System-Level Constraints
        Comprehensive Lower Bound Estimation from Behavi{*filter*}Descriptions

Timing Modeling and Simulation
        Fast and Accurate Timing Simulation with Regionwise Quadratic
                Models of MOS I-V Characteristics
        VLSI Timing Simulation with Selective Dynamic Regionization
        A New Efficient Approach to Statistical Delay Modeling
                of CMOS Digital Combinational Circuits

Clock and Routing Algorithms for High Performance Systems
        Simultaneous Driver and Wire Sizing
                for Performance and Power Optimization
        Low-Cost Single Layer Clock Trees with Exact Zero Elmore Delay Skew
        Clock-Period Constrained Minimal Buffer Insertion in Clock Trees

Retiming and Sequential Technology Mapping
        Efficient Implementation of Retiming
        Retiming with Non-Zero Clock Skew, Variable Register,
                and Interconnect Delay
        Optimal Latch Mapping and Retiming within a Tree

Issues in Discrete Simulation
        Simulation of Digital Circuits in the Presence of Uncertainty
        Fast Transient Power and Noise Estimation for CMOS VLSI Circuits
        The Inversion Algorithm for Digital Simulation

Technology CAD
        Unified Complete MOSFET Model for Analysis
                of Digital and Analog Circuits
        A Precorrected-FFT Method for Capacitance Extraction
                of Complicated 3-D Structures
        Measurement and Modeling of MOS Transistor Current Mismatch
                in Analog ICs

Minimizing Clock Skew
        Skew Sensitivity Minimization of Buffered Clock Tree
        Process-Variation-Tolerant Clock Skew Minimization
        A Specified Delay Accomplishing Clock Router using Multiple Layers

                 Sessions for Tuesday 8 November

Estimation Techniques for Power Consumption
        Switching Activity Analysis Considering Spatio-temp{*filter*}Correlations
        Estimation of Circuit Activity Considering Signal Correlations
                and Simultaneous Switching
        A Cell-Based Power Estimation in CMOS Combinational Circuits

Resource Binding
        Design Exploration for High-Performance Pipelines
        Simultaneous Functional-Unit Binding and Floorplanning
        Module Selection and Data Format Conversion
                for Cost-Optimal DSP Synthesis

Delay and Analog Testing
        On Testing Delay Faults in Macro-Based Combinational Circuits
        Raft: A Novel Program for Rapid-Fire Test and Diagnosis
                of Digital Logic for Marginal Delays and Delay Faults
        A Comprehensive Fault Macromodel for Op-Amps

Routing for FPGAs
        A Channel-Driven Global Routing with Consistent Placement
        A New Global Routing Algorithm for FPGAs
        On NP-Completeness of Regular 2-D FPGA Routing Architectures
                 and a Novel Solution

Optimization for Low Power
        A Symbolic Method to Reduce Power Consumption
                of Circuits Containing False Paths
        Multi-Level Network Optimization Targeting Low Power
        LP Based Cell Selection with Constraints of Timing, Area,
                and Power Consumption

Embedded Software
        Power Analysis of Embedded Software: A First Step Towards
                Software Power Minimization
        Generating Instruction Sets and Microarchitectures from Applications
        Register Assignment Through Resource Classification
                for ASIP Microcode Generation

PADE Based Circuit and Interconnect Analysis
        Efficient Small-Signal Circuit Analysis
                and Sensitivity Computations with the PVL Algorithm
        Capturing Time-of-Flight Delay for Transient Analysis
                Based on Scattering Parameter Macromodel
        RC Interconnect Synthesis - A Moment Fitting Approach

        Adaptive Cut Line Selection in Min-Cut Placement
                for Large Scale Sea-Of-Gates Arrays
        Folding a Stack of Equal Width Components
        Area Minimization for Hierarchical Floorplans

Formal Verification
        Multi-Level Synthesis for Safe Replaceability
        Iterative Algorithms for Formal Verification
                of Embedded Real-Time Systems
        Incremental Formal Design Verification

Timing Optimization by Gate Sizing
        Optimization of Critical Paths in Circuits with Level-Sensitive Latches
        Computing the Entire Active Area/Power Consumption vs. Delay Trade-Off
                Curve for Gate Sizing with a Piecewise Linear Simulator
        Dynamical Identification of Critical Paths for Iterative Gate Sizing

Analog and Mixed-Signal DFT
        Built-In Self-Test and Fault Diagnosis
                of Fully Differential Analogue Circuits
        A New Built-In-Self-Test Approach for Digital-to-Analog
                and Analog-to-Digital Converters
        Fault Detection and Input Stimulus Determination for
                the Testing of Analog Integrated Circuits
                Based on Power-Supply Current Monitoring

Modeling the Design Process
        An Enhanced Flow Model for Constraint Handling
                in Hierarchical Multi-View

read more »

Tue, 14 Jan 1997 07:34:37 GMT  
 12th ACM/IEEE International Conference on Computer-Aided Design

here is a simple question:

How do I suspend a $monitor(...) after it has started to print changes,
wait a specified amount of time and then continue to print changes?

Thanks in advance,


Dipl.-Ing. Jan Otterstedt
Laboratorium fuer Informationstechnologie      _/        _/_/_/_/  _/_/_/
Schneiderberg 32                              _/        _/          _/
D-30167 Hannover                             _/        _/_/_/      _/
Tel. +49-511-762-5049                       _/        _/          _/
Fax  +49-511-762-5051                      _/_/_/_/  _/        _/_/_/

#include <std_disclaimer.h>

Mon, 17 Feb 1997 00:59:09 GMT  
 [ 3 post ] 

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