Block SelectRAM+ and NCSim 
Author Message
 Block SelectRAM+ and NCSim

Hello everyone!

I'm a member of OPENCORES group and we are working on FREE IP PCI bridge
core.

I have a problem. I use NCSim and I can't seem to get primitives from XILINX
Spartan and Virtex working in it. We are trying to use Block SelectRAM+
cells for FIFO implementation.
I've compiled unisim and simprim libraries with NCVlog and got one warning
(log file doesn't show the reason) for each primitive in the library. When I
simulate FIFO design, all outputs are always HighZ, regardles of enable,
reset or any other signal. Does anyone know what to do?

Thanx!

Regards,
    Miha Dolenc

P.S.
    If anyone wants to help us out with actual core design please contat me
or visit our webpage
http://www.*-*-*.com/



Sun, 09 Nov 2003 15:43:49 GMT  
 
 [ 1 post ] 

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