A simple Verilog language question 
Author Message
 A simple Verilog language question

Hi Everyone,

for this line in Verilog

foo(.in({c_0,c_1,c_2,c_3},.out(out_bus));

where
module foo (in,out)
 input [0:3] in;
 output [0:3] out;

endmodule

My question is

which port does each c_x connect to? Say is it
c_0 ---> in[0] and so on?

The reason I ask is because I run into a similiar problem when using
Synopsys DC.

Thank you



Tue, 13 Apr 2004 12:43:40 GMT  
 A simple Verilog language question

Quote:

> for this line in Verilog
> foo(.in({c_0,c_1,c_2,c_3},.out(out_bus));
> where
> module foo (in,out)
>  input [0:3] in;
>  output [0:3] out;
> endmodule

> My question is
> which port does each c_x connect to? Say is it
> c_0 ---> in[0] and so on?
> The reason I ask is because I run into a similiar problem when using
> Synopsys DC.

Yes, they should connect in the order given. But i think this is
done wrong in one combination of release/HDL Compiler/Presto. I remember
an appnote on SolvIt. But i couldn't find it now.

Which version of DC do you use?
HDL Compiler or Presto?
What's going wrong exactly?

Lars
--
Address:  University of Mannheim; D7, 3-4; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Tue, 13 Apr 2004 15:01:51 GMT  
 
 [ 2 post ] 

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