VSIM Simulation Question 
Author Message
 VSIM Simulation Question

Hi all,

We are currently using VSIM to do verilog/vhdl co-simulation.
One of our verification engineers pointed out to me the other
day that we are getting DELTA values consistently in the range
of 20-25, whereas 5 is usually more the norm for RTL simulation.

This seems quite high to me and is slowing our RTL simulations
drastically.  I can't think of anywhere in the RTL code where
we are creating any sort of combinational feedback that could
cause such a high DELTA value.

Does anyone have any clues as to what else to look for that
could cause this to happen?

Steve Wood
Cisco Systems



Mon, 17 Jan 2000 03:00:00 GMT  
 VSIM Simulation Question

Quote:

> Hi all,

> We are currently using VSIM to do verilog/vhdl co-simulation.
> One of our verification engineers pointed out to me the other
> day that we are getting DELTA values consistently in the range
> of 20-25, whereas 5 is usually more the norm for RTL simulation.

> This seems quite high to me and is slowing our RTL simulations
> drastically.  I can't think of anywhere in the RTL code where
> we are creating any sort of combinational feedback that could
> cause such a high DELTA value.

> Does anyone have any clues as to what else to look for that
> could cause this to happen?

Look at the unit of the sim time to see if it is the unit you
expect, like ns.  If not ,then the timescale directive maybe the cause
of your problem.  In Verilog, simulation is run using the precision
unit, therefore, with
        `timescale      1ns/10ps

and
        and #(1,1)      .....

the simulation will be run at 10ps step, the delay #1 means 1ns.  It
will take a 100 "step" to finish.

If this is not the case, either there exists some timing annotation
in your design, e.g specify, or the environment, or the the glue
between the Verilog-VHDL err in unit conversion.

tan



Mon, 17 Jan 2000 03:00:00 GMT  
 VSIM Simulation Question

Quote:

> Hi all,

> We are currently using VSIM to do verilog/vhdl co-simulation.
> One of our verification engineers pointed out to me the other
> day that we are getting DELTA values consistently in the range
> of 20-25, whereas 5 is usually more the norm for RTL simulation.

> This seems quite high to me and is slowing our RTL simulations
> drastically.  I can't think of anywhere in the RTL code where
> we are creating any sort of combinational feedback that could
> cause such a high DELTA value.

> Does anyone have any clues as to what else to look for that
> could cause this to happen?

> Steve Wood
> Cisco Systems


Do you understand how the co-simulation works in your simulator ?

in one possible model for co-simulation the verilog and vhdl will have
seperate event queues
leading to considerable synchronization overhead. Most likely the two
event queues will be completely lock stepped delta cycle by delta cycle.
not sure there is a solution to this other than moving to a simulator
that
uses a single event queue.

another co-simulation overhead is pins that are actually bidirs or
percieved to be
bidirs by the software that appear at the co-simulation boundary. it may
take an iteration
between the two simulators for the values to settle.

One possible way for understanding what is going on at the boundary is
watch for 'transaction
on the boundary pins (in vhdl) and compare it to what would happen if it
were a unified
simulation in verilog or vhdl.

Your vendor may be able to give you a model of how the co-simulation
interface works. Understanding the interface and tuning your simulation
model to it might help.

--
regards,
 Ramesh
(Ramesh Narayanaswamy)



Tue, 18 Jan 2000 03:00:00 GMT  
 
 [ 3 post ] 

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