Verilog -> VHDL 
Author Message
 Verilog -> VHDL

                Hi,

over here we have some Verilog descriptions of ASIC's, which need to be
converted to VHDL descriptions.

The Verilog descriptions are hardware descriptions that can be synthesized
by Synopsys. I expect the same from the VHDL descriptions.

Is there some tool that does this conversion ?
Does it generate acceptable code (not too much expanded, readable ..) ?

By the way, I think that the fact that it concerns hardware that can be
synthesized, makes the translation job easier. (No tricky constructions,
limited number of processes ...)

Thanks.

Jos De Laender - Alcatel Bell - SH144  
Antwerpen - Belgium



Sat, 14 Sep 1996 00:24:39 GMT  
 Verilog -> VHDL


Quote:
>            Hi,

>over here we have some Verilog descriptions of ASIC's, which need to be
>converted to VHDL descriptions.

...
>Is there some tool that does this conversion ?
>Does it generate acceptable code (not too much expanded, readable ..) ?

...
>Jos De Laender - Alcatel Bell - SH144  
>Antwerpen - Belgium


--
Eli Sterheim
interHDL inc.
1270 Oakmead PkWy, #207
Sunnyvale, CA 94086
Tel (408) 749-8775
FAX (408) 749-8823



Sun, 15 Sep 1996 10:01:23 GMT  
 Verilog -> VHDL
You can also use Synopsys. If you have both the verilog and
vhdl compiler. You can read in the one (rtl) and set the
proper variables, defaults, and compiler directives, and then
export the other (rtl). Ask your AE. There are a few restrictions.

Peet



Sat, 21 Sep 1996 00:03:59 GMT  
 
 [ 3 post ] 

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