
verilog netlist -> spice netlist
You can simulate verilog and spice together. Or you can convert this to EPIC format.
See the manual on what formats Powermill supports.
Matt
Quote:
> I am currently working on a project which involve the power estimation
> of an embedded block by using Synopsys Powermill. I was wondering are
> there any solutions of converting the structural verilog netlist to a
> spice netlist? Thanks a lot.