strength keyword 
Author Message
 strength keyword

Can anyone tell me how the keyword "strength" is used in Verilog?  It's
a reserved keyword (at least in verilog-xl), but I can't find any
description of where I'd actually use it.  I know how to uses strengths,
but I'm just wondering how this specific keyword comes into play.

--
bob wood



Mon, 04 Feb 2002 03:00:00 GMT  
 strength keyword
Here is brief description for strength keyword from LRM.
I think it is a good idea to get a copy of LRM to get more details.

----------------
Strengths
There are two types of strengths that can be specified in a net
declaration. They are as follows:
? charge strength used when declaring a net of type trireg
? drive strength used when placing a continuous assignment
on a net in the same statement that declares the net

Gate declarations can also specify a drive strength. See Chapter 6, Gate
and Switch Level Modeling, for more information on gates and for
important information on strengths.
Synthesis Note: Drive strength and charge strength are optional-abort
for
synthesis.

Charge Strength
The <charge_strength> specification can be used only with trireg
nets. A trireg net is used to model charge storage; <charge_strength>
specifies the relative size of the capacitance. The <CAPACITOR_SIZE>
declaration is one of the following keywords:
?small
?medium
?large
When no size is specified in a trireg declaration, its size is medium.
The following is a syntax example of a strength declaration:

trireg (small) st1 ;

A trireg net can model a charge storage node whose charge decays
over time. The simulation time of a charge decay is specified in the
trireg nets delay specification

Drive Strength
The <drive_strength> specification allows a continuous assignment to be
placed on a net in the same statement that declares that net.
See Chapter 5, Assignments, for more details.
Net strength properties are described in detail in Chapter 6, Gate and
Switch Level Modeling.
-----------------------
Hope this helps.
Rajesh Ba{*filter*}ule

Visit Verilog FAQ : http://www.*-*-*.com/
and Verilog Page: http://www.*-*-*.com/


Quote:

> Can anyone tell me how the keyword "strength" is used in Verilog?
It's
> a reserved keyword (at least in verilog-xl), but I can't find any
> description of where I'd actually use it.  I know how to uses
strengths,
> but I'm just wondering how this specific keyword comes into play.

> --
> bob wood


http://www.*-*-*.com/ ~wood

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Sun, 10 Feb 2002 03:00:00 GMT  
 strength keyword
Quote:

> Here is brief description for strength keyword from LRM.

<snip>

Thanks for the info, but I didn't see anything in your message that
actually describes the reserved keyword "strength".  I understand
how to specify charge strength and drive strength, but I'm wondering
where I would ever actually code the word "strength".

--
bob wood



Sun, 10 Feb 2002 03:00:00 GMT  
 strength keyword

Quote:

> Can anyone tell me how the keyword "strength" is used in Verilog?
It's
> a reserved keyword (at least in verilog-xl), but I can't find any
> description of where I'd actually use it.  I know how to uses
strengths,
> but I'm just wondering how this specific keyword comes into play.

> --
> bob wood


http://www.ziplink.net/~wood

   I would first like to ask you how did you find
   out that "strength" is a reserved keyword
   (e.g. trying something like "reg strength;"
   gave an error etc.) ? I checked up both IEEE
   1364-1995 and Draft 2 of 1364-1999, but none
   of them had "strength" described as keyword. You
   may still want to check OVI LRM2.0. But
   first make sure this is really a keyword (i.e.
   apart from the keyword list, it also appears
   as a terminal symbol in the Verilog BNF).

   Regards,
   - Swapnajit.
--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
 Principles of Verilog PLI -By- Swapnajit Mittra
 Kluwer Academic Publishers. ISBN: 0-7923-8477-6
 http://www.angelfire.com/ca/verilog/

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Sun, 10 Feb 2002 03:00:00 GMT  
 strength keyword

Quote:

>    I would first like to ask you how did you find
>    out that "strength" is a reserved keyword.

I found the "strength" word in some old Cadence documentation.  I've
verified that Verilog-XL 2.5 gives me an error if I try to create
a net or wire named "strength".  But as a few people have mentioned,
the word "strength" doesn't show up in the Formal Language Definition.
That's the whole reason for my question... Verilog-XL seems to consider
this a reserved word, but I can't find any documentation of where it
would be used.  For whatever reason, I assume this is a Cadence
anomaly.

--
bob wood



Mon, 11 Feb 2002 03:00:00 GMT  
 
 [ 5 post ] 

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