Wide shift register implementation
Author Message
Wide shift register implementation

A sensible architecture (easy to read, easy to follow...) for a shift
register of width 8 and depth 16 would be to create a 2-dimensional array
and use a loop to do the shifting (at every clock.)  However, from what I
have been reading about verilog (I'm a little rusty, having done VHDL the
last 3+ years), you can't do this:  you can't use a loop with an index
variable to do the new value assignments, such as data[i][7:0] <=
data[8-1][7:0].  Is there a clean way to do this, without the brute force
method of unwrapping the loop?

Jason
Jason T. Wright
Cygnion Corp

Sun, 02 Mar 2003 02:21:33 GMT
Wide shift register implementation

Quote:
>A sensible architecture (easy to read, easy to follow...) for a shift
>register of width 8 and depth 16 would be to create a 2-dimensional array
>and use a loop to do the shifting (at every clock.)  However, from what I
>have been reading about verilog (I'm a little rusty, having done VHDL the
>last 3+ years), you can't do this:  you can't use a loop with an index
>variable to do the new value assignments, such as data[i][7:0] <=
>data[8-1][7:0].  Is there a clean way to do this, without the brute force
>method of unwrapping the loop?

Jason,

A little unclear as to what you're trying to accomplish - but I'll
take a stab.  At a clk, your're trying to shift each of 16 8-bit registers left
one?  If so:

reg [ 4:0 ] i;
reg [ 7:0 ] regarray [ 0 : 15 ];

if( shift )
for( i = 0; i < 16; i = i + 1 )
regarray[ i ] <= regarray[ i ] << 1;

Or you'll only shifting one specific one at the clock?
reg [ 3:0 ] whichreg;

if( shift )
regarray[ whichreg ] <= regarray[ whichreg ] << 1;

If you're doing something more complex with the bits, then
you'll likely need to assign the index'd element to a
temporary variable first, and then pick off the bits there.
As you've probably become aware, in verilog you can't reference
specific bits of an array directly.

Regards,

Mark

--
Mark Curry

Remove the animal(s) from the domain name to reply

Sun, 02 Mar 2003 02:55:09 GMT
Wide shift register implementation
Thanks, Mark.  Your first example is exactly what I wanted to do (other
than the asynchronous reset.)  I was starting to write the verilog, but I
had some questions on the syntax.  I was researching Deja News, as well as
looking in a Verilog textbook, and got the impression that you couldn't do
it that way.

Jason

Quote:

>>A sensible architecture (easy to read, easy to follow...) for a shift
>>register of width 8 and depth 16 would be to create a 2-dimensional array
>>and use a loop to do the shifting (at every clock.)  However, from what I
>>have been reading about verilog (I'm a little rusty, having done VHDL the
>>last 3+ years), you can't do this:  you can't use a loop with an index
>>variable to do the new value assignments, such as data[i][7:0] <=
>>data[8-1][7:0].  Is there a clean way to do this, without the brute force
>>method of unwrapping the loop?

>Jason,

>A little unclear as to what you're trying to accomplish - but I'll
>take a stab.  At a clk, your're trying to shift each of 16 8-bit registers left
>one?  If so:

>reg [ 4:0 ] i;
>reg [ 7:0 ] regarray [ 0 : 15 ];

>  if( shift )
>    for( i = 0; i < 16; i = i + 1 )
>      regarray[ i ] <= regarray[ i ] << 1;

>Or you'll only shifting one specific one at the clock?
>reg [ 3:0 ] whichreg;

>  if( shift )
>    regarray[ whichreg ] <= regarray[ whichreg ] << 1;

>If you're doing something more complex with the bits, then
>you'll likely need to assign the index'd element to a
>temporary variable first, and then pick off the bits there.
>As you've probably become aware, in verilog you can't reference
>specific bits of an array directly.

>Regards,

>Mark

>--
>Mark Curry

>Remove the animal(s) from the domain name to reply

Jason T. Wright
Cygnion Corp

Sun, 02 Mar 2003 04:16:35 GMT
Wide shift register implementation

Quote:

> >A sensible architecture (easy to read, easy to follow...) for a shift
> >register of width 8 and depth 16 would be to create a 2-dimensional array
> >and use a loop to do the shifting (at every clock.)  However, from what I
> >have been reading about verilog (I'm a little rusty, having done VHDL the
> >last 3+ years), you can't do this:  you can't use a loop with an index
> >variable to do the new value assignments, such as data[i][7:0] <=
> >data[8-1][7:0].  Is there a clean way to do this, without the brute force
> >method of unwrapping the loop?

> Jason,

> A little unclear as to what you're trying to accomplish - but I'll
> take a stab.  At a clk, your're trying to shift each of 16 8-bit registers left
> one?  If so:

> reg [ 4:0 ] i;
> reg [ 7:0 ] regarray [ 0 : 15 ];

>   if( shift )
>     for( i = 0; i < 16; i = i + 1 )
>       regarray[ i ] <= regarray[ i ] << 1;

actually I suspect he wanted something more like

reg [ 4:0 ] i;
reg [ 7:0 ] regarray [ 0 : 15 ];

if( shift ) begin
for( i = 0; i < 15; i = i + 1 )
regarray[ i+1 ] <= regarray[ i ];
regarray[0] <= in;
end

(a 16-entry 8-biut wide shift register)

You can also do it with bit vectors:

parameter  NENTRIES=16;
parameter WIDTH=8;

reg     [(WIDTH*NENTRIES)-1:0]shiftreg;
input   [WIDTH-1:0]in;
output  [WIDTH-1:0]out;
assign  out = shiftreg[(WIDTH*NENTRIES)-1:(WIDTH*NENTRIES)-WIDTH];

if (shift)
shift_reg <= {shiftreg[(WIDTH*(NENTRIES-1))-1], in};

which is probably also more likely to be synthesizable
(depending of course on how smart your synthesis tool is).

Paul Campbell

Sun, 02 Mar 2003 12:21:22 GMT
Wide shift register implementation
<snip>

Quote:

> One note on Paul's comment on synthesizability.  I'm sure
> he was referring to the for loops.  I try to avoid 'em
> at all cost, but at times, there just impossible
> to avoid.  So far, I've had no trouble with Synopys
> and for loops.  So long as the loop can be unrolled
> at compile time, things are ok.  Does anyone
> else have any comments on using for loops with
> other synthesis tools?  Does it work ok?

> Just curious.  I try not to code with implicit
> tool dependability....

I've used for-loops with Synplify and they work well: efficient,
fast logic which is sizable via parameters.

Honestly, though, I haven't benchmarked against the same
circuits with unrolled loops. I haven't needed to.

Marc

Sun, 02 Mar 2003 03:00:00 GMT
Wide shift register implementation
I hasd a chunk of code that used a for loop to hook up a shift register
output with
to a xor gate along with a reference code. Ambit and  leonardo
synthesized it just
fine but Xilinx verilog complier just couldn't figure it out. I had to
write out all of the
assign statements myself. Here's a sample of the code that was
rewritten:

for (i=1; i<=125; i=i+2) begin
if (i == 1)
begin
srvec0[0] = (sreg0[1] ^ pnvec[0]);
srvec1[0] = (sreg1[1] ^ pnvec[0]);
srvec0[63] = ((sreg0[127] ^ pnvec[63])) & _128;
srvec1[63] = ((sreg1[127] ^ pnvec[63])) & _128;
end
else
begin
srvec0[((i-1)/2)] = (sreg0[i] ^ pnvec[(i-1)/2]);
srvec1[((i-1)/2)] = (sreg1[i] ^ pnvec[(i-1)/2]);
end
end
end

regards
Jerry

Quote:

> <snip>

> > One note on Paul's comment on synthesizability.  I'm sure
> > he was referring to the for loops.  I try to avoid 'em
> > at all cost, but at times, there just impossible
> > to avoid.  So far, I've had no trouble with Synopys
> > and for loops.  So long as the loop can be unrolled
> > at compile time, things are ok.  Does anyone
> > else have any comments on using for loops with
> > other synthesis tools?  Does it work ok?

> > Just curious.  I try not to code with implicit
> > tool dependability....

> I've used for-loops with Synplify and they work well: efficient,
> fast logic which is sizable via parameters.

> Honestly, though, I haven't benchmarked against the same
> circuits with unrolled loops. I haven't needed to.

> Marc

Sun, 02 Mar 2003 03:00:00 GMT
Wide shift register implementation

Quote:

>> >A sensible architecture (easy to read, easy to follow...) for a shift
>> >register of width 8 and depth 16 would be to create a 2-dimensional array
>> >and use a loop to do the shifting (at every clock.)  However, from what I
>> >have been reading about verilog (I'm a little rusty, having done VHDL the
>> >last 3+ years), you can't do this:  you can't use a loop with an index
>> >variable to do the new value assignments, such as data[i][7:0] <=
>> >data[8-1][7:0].  Is there a clean way to do this, without the brute force
>> >method of unwrapping the loop?

>> Jason,

>> A little unclear as to what you're trying to accomplish - but I'll
>> take a stab.  At a clk, your're trying to shift each of 16 8-bit registers left
>> one?  If so:

>> reg [ 4:0 ] i;
>> reg [ 7:0 ] regarray [ 0 : 15 ];

>>   if( shift )
>>     for( i = 0; i < 16; i = i + 1 )
>>       regarray[ i ] <= regarray[ i ] << 1;

>actually I suspect he wanted something more like

>  reg [ 4:0 ] i;
>  reg [ 7:0 ] regarray [ 0 : 15 ];

>    if( shift ) begin
>      for( i = 0; i < 15; i = i + 1 )
>        regarray[ i+1 ] <= regarray[ i ];
>      regarray[0] <= in;
>    end

>(a 16-entry 8-biut wide shift register)

>You can also do it with bit vectors:

>    parameter  NENTRIES=16;
>    parameter WIDTH=8;

>    reg     [(WIDTH*NENTRIES)-1:0]shiftreg;
>    input   [WIDTH-1:0]in;
>    output  [WIDTH-1:0]out;
>    assign  out = shiftreg[(WIDTH*NENTRIES)-1:(WIDTH*NENTRIES)-WIDTH];

>    if (shift)
>      shift_reg <= {shiftreg[(WIDTH*(NENTRIES-1))-1], in};

>which is probably also more likely to be synthesizable
>(depending of course on how smart your synthesis tool is).

Paul, now that I think about it, you're probably right with what
Jason's intending.  Jason, even though you thought
my original response was what you wanted - think it through
again - I think Paul's got it right.

One note on Paul's comment on synthesizability.  I'm sure
he was referring to the for loops.  I try to avoid 'em
at all cost, but at times, there just impossible
to avoid.  So far, I've had no trouble with Synopys
and for loops.  So long as the loop can be unrolled
at compile time, things are ok.  Does anyone
else have any comments on using for loops with
other synthesis tools?  Does it work ok?

Just curious.  I try not to code with implicit
tool dependability....

Regards,

Mark

--
Mark Curry

Remove the animal(s) from the domain name to reply

Sun, 02 Mar 2003 23:37:02 GMT

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