HELP: Verilog doesn't compile 
Author Message
 HELP: Verilog doesn't compile

I put the following code into a Verilog module and tried to compile
it.

module  add24s (a, b, clk, nrst, sum);
   input [23:0] a ; wire [23:0] a ;
   input [22:0] b ; wire [22:0] b ;
   input clk ; wire clk ;
   input nrst ; wire nrst ;
   output [24:0] sum ; reg [24:0] sum ;

        wire [24:0] tempsum;

        assign tempsum = {a[23],a}+{2{b[22]},b};


        begin
                if (!nrst)
                        sum <= 25'd0;
                else
                        sum <= tempsum;
        end
endmodule

The compiler errors and says

ERROR: Syntax error: unexpected symbol:',' in cst1:add24s #25
ERROR: Syntax error: unexpected symbol:'}' in cst1:add24s #25

I'm just trying to sign extend signal a by one bit and signal b by two
bits.  My Verilog text does seem to differentiate between "braces" for
concatenation and "brackets" for replication but I don't see how they
differ with respect to what I have available on a standard keyboard.

Any thoughts/ideas?

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Mon, 11 Feb 2002 03:00:00 GMT  
 HELP: Verilog doesn't compile
Hi,
Major Problem seems to be in...

assign tempsum = {a[23],a}+{2{b[22]},b};

I dont know what are you are trying to do here??

But if you insist on doing this then.....do something like this.

assign tmp1={a[23],a};
assign tmp2={b[22],b[22],b};


         begin
                 if (!nrst)
                         sum = 0;
                 else
                         sum = tmp1+tmp2;
        end
endmodule

PS: check for type i.e. wire, reg.

Azhar

Quote:

> I put the following code into a Verilog module and tried to compile
> it.

> module  add24s (a, b, clk, nrst, sum);
>    input [23:0] a ; wire [23:0] a ;
>    input [22:0] b ; wire [22:0] b ;
>    input clk ; wire clk ;
>    input nrst ; wire nrst ;
>    output [24:0] sum ; reg [24:0] sum ;

>         wire [24:0] tempsum;

>         assign tempsum = {a[23],a}+{2{b[22]},b};


>         begin
>                 if (!nrst)
>                         sum <= 25'd0;
>                 else
>                         sum <= tempsum;
>         end
> endmodule

> The compiler errors and says

> ERROR: Syntax error: unexpected symbol:',' in cst1:add24s #25
> ERROR: Syntax error: unexpected symbol:'}' in cst1:add24s #25

> I'm just trying to sign extend signal a by one bit and signal b by two
> bits.  My Verilog text does seem to differentiate between "braces" for
> concatenation and "brackets" for replication but I don't see how they
> differ with respect to what I have available on a standard keyboard.

> Any thoughts/ideas?

> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.



Mon, 11 Feb 2002 03:00:00 GMT  
 HELP: Verilog doesn't compile
The problem is in your replication operator. It's just missing
a pair of brackets.

assign tempsum = {a[23],a}+{{2{b[22]}},b};

Awkward, but necessary for combining catenation
and replication.

: I put the following code into a Verilog module and tried to compile
: it.

: module  add24s (a, b, clk, nrst, sum);
:    input [23:0] a ; wire [23:0] a ;
:    input [22:0] b ; wire [22:0] b ;
:    input clk ; wire clk ;
:    input nrst ; wire nrst ;
:    output [24:0] sum ; reg [24:0] sum ;

:         wire [24:0] tempsum;

:         assign tempsum = {a[23],a}+{2{b[22]},b};


:         begin
:                 if (!nrst)
:                         sum <= 25'd0;
:                 else
:                         sum <= tempsum;
:         end
: endmodule

: The compiler errors and says

: ERROR: Syntax error: unexpected symbol:',' in cst1:add24s #25
: ERROR: Syntax error: unexpected symbol:'}' in cst1:add24s #25

: I'm just trying to sign extend signal a by one bit and signal b by two
: bits.  My Verilog text does seem to differentiate between "braces" for
: concatenation and "brackets" for replication but I don't see how they
: differ with respect to what I have available on a standard keyboard.

: Any thoughts/ideas?

: Sent via Deja.com http://www.deja.com/
: Share what you know. Learn what you don't.



Mon, 11 Feb 2002 03:00:00 GMT  
 
 [ 3 post ] 

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