Multiple Clock design, setup & hold time violation 
Author Message
 Multiple Clock design, setup & hold time violation

Quote:
> Hi all,

> For my design, there is a global clock, some input signals,  some output
> signals (clocked by external source).

> When input signals come in(synchronized by global clock), the central
> controller will collect, organize, manipulate & store in buffer.
> The output port interface portion will at intervals (ctrl by external clk)
> request data from buffer.
> During my design, I encounter hundreds of design warning by  max+plus2
(i'm
> using synplify vhdl sythesizer) saying sth like this
> "Design Dr warning: flipflop or synchronous memory 'q_data_7' receives
data
> that is synchronized by another clock at flipflop or synchronous memory
> 'subc_datareq'   "
>     &
> "Design Dr warning: inverting delay chain starting at primitive
> 'cntr_1_lut_5'  feeds primitive 'statemachine_cntr_i_0' "

> & my project fails to work during timing simulation.
> Can somebody pls shed some light on how to properly design a multiple
clock
> system that meets all setup time, hold time....???
> or is there any good reference that stress on this area of design?

> Any help is much appreciated.  Thanks in advance.

> Rgds
> MK



Sat, 28 Sep 2002 03:00:00 GMT  
 Multiple Clock design, setup & hold time violation
Hi!

I have a few modules that works in this way...
In_module which works at .. say 33Mhz( f), out_module at ard 2MHz ( f/16). I
have synchornized the out_module to in_module and the warning goes away...
and yup! The simulation result is now correct :-))
but I suffer some delay(1-2 clk cycles) in sending data... :-(

There is another out2_module that works at much higher speed, (max f/3 or
11MHz). I believe my method no longer works since the delay (1-2 clk cycles)
is intolerable in this case... Does yer method work in this case?

btw, in Synplify, I managed to design all my modules to work at, say all

Quote:
>70Mhz. But when I use schematic to interconnect the modules in max+plus2

(use fast logic synthesis), after compilation, the max frequency drops
drastically to ard 40MHz.... is there any way to improve the final max
frequency close to 70MHz??

Thanks Iglasner & Christian for sharing yer experiences... They're useful
for novice like me :-)

Regards
MK


Quote:
> Hi,

>    You ommite the clock frequance of the 2 clock's (or maybe more ?)
> you are talking about as well as are the infomation delay is crusial or
> can you wait a clock or two.

> according to the above  there are few way to approch the problem.

> as an example assume you have a data stored in module1 work with clk1
> in few buffers and you want to read a certain buffer to a module2 that
> work in clk2

> than a general sulotion will be that module2 will prepare the buffer
> number he want to read and than will rais a single saying he want to
> read.

> this read signal you will pass through syncronizer (to clk1) to module1
> domain and than module1 will look and see the address which is
> already "long ago" stable.

> module1 will than put the data and will rais a signal saying data is
> ready.

> this data is ready signal will also be syncronize (to clk2) and when
> module2 see it the data is already stable, and can be "used safely".

> than module 2 pulldown the read and as soon as mosule 1 see that the
> read signal is pulldown he pulldown the data is ready signal.

> this is just one way (usually called full-handshake) and there are many
> other.

> have a nice day

>    Illan



> > Hi all,

> > For my design, there is a global clock, some input signals,  some
> output
> > signals (clocked by external source).

> > When input signals come in(synchronized by global clock), the central
> > controller will collect, organize, manipulate & store in buffer.
> > The output port interface portion will at intervals (ctrl by external
> clk)
> > request data from buffer.
> > During my design, I encounter hundreds of design warning by
> max+plus2 (i'm
> > using synplify vhdl sythesizer) saying sth like this
> > "Design Dr warning: flipflop or synchronous memory 'q_data_7'
> receives data
> > that is synchronized by another clock at flipflop or synchronous
> memory
> > 'subc_datareq'   "
> >     &
> > "Design Dr warning: inverting delay chain starting at primitive
> > 'cntr_1_lut_5'  feeds primitive 'statemachine_cntr_i_0' "

> > & my project fails to work during timing simulation.
> > Can somebody pls shed some light on how to properly design a multiple
> clock
> > system that meets all setup time, hold time....???
> > or is there any good reference that stress on this area of design?

> > Any help is much appreciated.  Thanks in advance.

> > Rgds
> > MK

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Sun, 29 Sep 2002 03:00:00 GMT  
 Multiple Clock design, setup & hold time violation
First, it is possible you are adding relatively long combinatorial delays when
you connect the modules together, or you may be loading down a signal with too
high a fanout.  That can be mitigated somwhat by duplicating logic.

You may be filling the device up to where routing congestion gets in the way and
slows it down.  The Altera devices are vulnerable to this phenomenon, especially
in heavily data path and arithmetic designs because of the routing structure.
Here, about all that really helps is going to a different design approach.  You
can go to a larger device, but you won't get the same speeds for your modules
there (see below).

Also be aware that the Altera line slows down as you go to bigger devices in the
same family/speed grade, again due to the routing resources.

Without knowing more about your design, it is hard to say what the exact problem
is.

Quote:

> Hi!

> I have a few modules that works in this way...
> In_module which works at .. say 33Mhz( f), out_module at ard 2MHz ( f/16). I
> have synchornized the out_module to in_module and the warning goes away...
> and yup! The simulation result is now correct :-))
> but I suffer some delay(1-2 clk cycles) in sending data... :-(

> There is another out2_module that works at much higher speed, (max f/3 or
> 11MHz). I believe my method no longer works since the delay (1-2 clk cycles)
> is intolerable in this case... Does yer method work in this case?

> btw, in Synplify, I managed to design all my modules to work at, say all
> >70Mhz. But when I use schematic to interconnect the modules in max+plus2
> (use fast logic synthesis), after compilation, the max frequency drops
> drastically to ard 40MHz.... is there any way to improve the final max
> frequency close to 70MHz??

> Thanks Iglasner & Christian for sharing yer experiences... They're useful
> for novice like me :-)

> Regards
> MK



> > Hi,

> >    You ommite the clock frequance of the 2 clock's (or maybe more ?)
> > you are talking about as well as are the infomation delay is crusial or
> > can you wait a clock or two.

> > according to the above  there are few way to approch the problem.

> > as an example assume you have a data stored in module1 work with clk1
> > in few buffers and you want to read a certain buffer to a module2 that
> > work in clk2

> > than a general sulotion will be that module2 will prepare the buffer
> > number he want to read and than will rais a single saying he want to
> > read.

> > this read signal you will pass through syncronizer (to clk1) to module1
> > domain and than module1 will look and see the address which is
> > already "long ago" stable.

> > module1 will than put the data and will rais a signal saying data is
> > ready.

> > this data is ready signal will also be syncronize (to clk2) and when
> > module2 see it the data is already stable, and can be "used safely".

> > than module 2 pulldown the read and as soon as mosule 1 see that the
> > read signal is pulldown he pulldown the data is ready signal.

> > this is just one way (usually called full-handshake) and there are many
> > other.

> > have a nice day

> >    Illan



> > > Hi all,

> > > For my design, there is a global clock, some input signals,  some
> > output
> > > signals (clocked by external source).

> > > When input signals come in(synchronized by global clock), the central
> > > controller will collect, organize, manipulate & store in buffer.
> > > The output port interface portion will at intervals (ctrl by external
> > clk)
> > > request data from buffer.
> > > During my design, I encounter hundreds of design warning by
> > max+plus2 (i'm
> > > using synplify vhdl sythesizer) saying sth like this
> > > "Design Dr warning: flipflop or synchronous memory 'q_data_7'
> > receives data
> > > that is synchronized by another clock at flipflop or synchronous
> > memory
> > > 'subc_datareq'   "
> > >     &
> > > "Design Dr warning: inverting delay chain starting at primitive
> > > 'cntr_1_lut_5'  feeds primitive 'statemachine_cntr_i_0' "

> > > & my project fails to work during timing simulation.
> > > Can somebody pls shed some light on how to properly design a multiple
> > clock
> > > system that meets all setup time, hold time....???
> > > or is there any good reference that stress on this area of design?

> > > Any help is much appreciated.  Thanks in advance.

> > > Rgds
> > > MK

> > Sent via Deja.com http://www.deja.com/
> > Before you buy.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://users.ids.net/~randraka


Sun, 29 Sep 2002 03:00:00 GMT  
 Multiple Clock design, setup & hold time violation
Hi,

  you mention that you have low freq which are f/16, IF this low freq
is generate from the base freq (f) than you might not need the
syncronizer at all BUT here come the tricky quesiton, how do you
generate the low freq ?

if you have a counter/devider than depend on the way you designed this
devide, if you design is such as that both posedge of the low freq and
high freq are togther (a cascade DFF as a simple counter therfore will
not do) than when you send a signla from the low freq to the high the
signal not need to have any "handling" HOWEVER when you send from the
high to the low than you must hold it for few clock so it will still be
active when the low freq finaly get to the posedge. (if you also use
negedge of clock somewhere you will need that also both negedge of the
clock will be on the same time).

BTW the "suffer" of clock delay is expected as after all you sample it
twice in the syncronizer.

also you might consider not a full-handshake incase you are certain
that the other module "saw" the signla, and in this case you can de-
active the signal as soon as you belive it is ok.

unless you are limited due to number of FF/gates I belive this will
work also in higher frequance, what you might consider doing but is all
depend on your desing is that you might consider adding a fifo, or
maybe make the data passing as burst mode meaning that when you ask to
read the data you also tell how many read you want to do in this read
(the how many will be treated as data and not need to be syncronized)
and than you can get few block of data but again it is all just an
idea's and it all depoend on your design.

have a nice day

  Illan



Quote:
> Hi!

> I have a few modules that works in this way...
> In_module which works at .. say 33Mhz( f), out_module at ard 2MHz (
f/16). I
> have synchornized the out_module to in_module and the warning goes
away...
> and yup! The simulation result is now correct :-))
> but I suffer some delay(1-2 clk cycles) in sending data... :-(

> There is another out2_module that works at much higher speed, (max
f/3 or
> 11MHz). I believe my method no longer works since the delay (1-2 clk
cycles)
> is intolerable in this case... Does yer method work in this case?

> btw, in Synplify, I managed to design all my modules to work at, say
all
> >70Mhz. But when I use schematic to interconnect the modules in
max+plus2
> (use fast logic synthesis), after compilation, the max frequency drops
> drastically to ard 40MHz.... is there any way to improve the final max
> frequency close to 70MHz??

> Thanks Iglasner & Christian for sharing yer experiences... They're
useful
> for novice like me :-)

> Regards
> MK



> > Hi,

> >    You ommite the clock frequance of the 2 clock's (or maybe more ?)
> > you are talking about as well as are the infomation delay is
crusial or
> > can you wait a clock or two.

> > according to the above  there are few way to approch the problem.

> > as an example assume you have a data stored in module1 work with
clk1
> > in few buffers and you want to read a certain buffer to a module2
that
> > work in clk2

> > than a general sulotion will be that module2 will prepare the buffer
> > number he want to read and than will rais a single saying he want to
> > read.

> > this read signal you will pass through syncronizer (to clk1) to
module1
> > domain and than module1 will look and see the address which is
> > already "long ago" stable.

> > module1 will than put the data and will rais a signal saying data is
> > ready.

> > this data is ready signal will also be syncronize (to clk2) and when
> > module2 see it the data is already stable, and can be "used safely".

> > than module 2 pulldown the read and as soon as mosule 1 see that the
> > read signal is pulldown he pulldown the data is ready signal.

> > this is just one way (usually called full-handshake) and there are
many
> > other.

> > have a nice day

> >    Illan



> > > Hi all,

> > > For my design, there is a global clock, some input signals,  some
> > output
> > > signals (clocked by external source).

> > > When input signals come in(synchronized by global clock), the
central
> > > controller will collect, organize, manipulate & store in buffer.
> > > The output port interface portion will at intervals (ctrl by
external
> > clk)
> > > request data from buffer.
> > > During my design, I encounter hundreds of design warning by
> > max+plus2 (i'm
> > > using synplify vhdl sythesizer) saying sth like this
> > > "Design Dr warning: flipflop or synchronous memory 'q_data_7'
> > receives data
> > > that is synchronized by another clock at flipflop or synchronous
> > memory
> > > 'subc_datareq'   "
> > >     &
> > > "Design Dr warning: inverting delay chain starting at primitive
> > > 'cntr_1_lut_5'  feeds primitive 'statemachine_cntr_i_0' "

> > > & my project fails to work during timing simulation.
> > > Can somebody pls shed some light on how to properly design a
multiple
> > clock
> > > system that meets all setup time, hold time....???
> > > or is there any good reference that stress on this area of design?

> > > Any help is much appreciated.  Thanks in advance.

> > > Rgds
> > > MK

> > Sent via Deja.com http://www.deja.com/
> > Before you buy.

Sent via Deja.com http://www.deja.com/
Before you buy.


Sun, 29 Sep 2002 03:00:00 GMT  
 Multiple Clock design, setup & hold time violation

Quote:

> Hi!

> I have a few modules that works in this way...
> In_module which works at .. say 33Mhz( f), out_module at ard 2MHz ( f/16). I
> have synchornized the out_module to in_module and the warning goes away...
> and yup! The simulation result is now correct :-))
> but I suffer some delay(1-2 clk cycles) in sending data... :-(

> There is another out2_module that works at much higher speed, (max f/3 or
> 11MHz). I believe my method no longer works since the delay (1-2 clk cycles)
> is intolerable in this case... Does yer method work in this case?

You are writing "f" and "f/16". Are these frequencies synchronous,
that is, is that f/16 created from f by division? In this case,
it would be much easier and better to feed the higher frequency to all
modules and to do the "frequency division" by distributing a f/16
clock-enable signal.

This would be a fully synchronous design, and all synchronization
problems would be solved, maybe (but not necessarily) at the cost of
higher logic consumption.

Quote:
> btw, in Synplify, I managed to design all my modules to work at, say all
> >70Mhz. But when I use schematic to interconnect the modules in max+plus2
> (use fast logic synthesis), after compilation, the max frequency drops
> drastically to ard 40MHz.... is there any way to improve the final max
> frequency close to 70MHz??

This is very hard to tell without knowing more about the whole
design. The timing analyzer might help you to find the specific signal
that needs that 25ns.

chm.

--

utanet.at  -  Vienna/Austria/Europe



Sun, 29 Sep 2002 03:00:00 GMT  
 Multiple Clock design, setup & hold time violation
Hi,

The f/16 is from external source, so I believe the safest way is to have it
synchronized with f , have full handshake and suffer some delay....
I simply don't have that experience to ensure everything works fine if I
don't use the safest method.

Illan, Thanks for all your ideas man.... i'll keep them in mind in my future
designs if I happen to encounter the similar deisgn problem again :-)))

MK


Quote:
> Hi,

>   you mention that you have low freq which are f/16, IF this low freq
> is generate from the base freq (f) than you might not need the
> syncronizer at all BUT here come the tricky quesiton, how do you
> generate the low freq ?

> if you have a counter/devider than depend on the way you designed this
> devide, if you design is such as that both posedge of the low freq and
> high freq are togther (a cascade DFF as a simple counter therfore will
> not do) than when you send a signla from the low freq to the high the
> signal not need to have any "handling" HOWEVER when you send from the
> high to the low than you must hold it for few clock so it will still be
> active when the low freq finaly get to the posedge. (if you also use
> negedge of clock somewhere you will need that also both negedge of the
> clock will be on the same time).

> BTW the "suffer" of clock delay is expected as after all you sample it
> twice in the syncronizer.

> also you might consider not a full-handshake incase you are certain
> that the other module "saw" the signla, and in this case you can de-
> active the signal as soon as you belive it is ok.

> unless you are limited due to number of FF/gates I belive this will
> work also in higher frequance, what you might consider doing but is all
> depend on your desing is that you might consider adding a fifo, or
> maybe make the data passing as burst mode meaning that when you ask to
> read the data you also tell how many read you want to do in this read
> (the how many will be treated as data and not need to be syncronized)
> and than you can get few block of data but again it is all just an
> idea's and it all depoend on your design.

> have a nice day

>   Illan



> > Hi!

> > I have a few modules that works in this way...
> > In_module which works at .. say 33Mhz( f), out_module at ard 2MHz (
> f/16). I
> > have synchornized the out_module to in_module and the warning goes
> away...
> > and yup! The simulation result is now correct :-))
> > but I suffer some delay(1-2 clk cycles) in sending data... :-(

> > There is another out2_module that works at much higher speed, (max
> f/3 or
> > 11MHz). I believe my method no longer works since the delay (1-2 clk
> cycles)
> > is intolerable in this case... Does yer method work in this case?

> > btw, in Synplify, I managed to design all my modules to work at, say
> all
> > >70Mhz. But when I use schematic to interconnect the modules in
> max+plus2
> > (use fast logic synthesis), after compilation, the max frequency drops
> > drastically to ard 40MHz.... is there any way to improve the final max
> > frequency close to 70MHz??

> > Thanks Iglasner & Christian for sharing yer experiences... They're
> useful
> > for novice like me :-)

> > Regards
> > MK



> > > Hi,

> > >    You ommite the clock frequance of the 2 clock's (or maybe more ?)
> > > you are talking about as well as are the infomation delay is
> crusial or
> > > can you wait a clock or two.

> > > according to the above  there are few way to approch the problem.

> > > as an example assume you have a data stored in module1 work with
> clk1
> > > in few buffers and you want to read a certain buffer to a module2
> that
> > > work in clk2

> > > than a general sulotion will be that module2 will prepare the buffer
> > > number he want to read and than will rais a single saying he want to
> > > read.

> > > this read signal you will pass through syncronizer (to clk1) to
> module1
> > > domain and than module1 will look and see the address which is
> > > already "long ago" stable.

> > > module1 will than put the data and will rais a signal saying data is
> > > ready.

> > > this data is ready signal will also be syncronize (to clk2) and when
> > > module2 see it the data is already stable, and can be "used safely".

> > > than module 2 pulldown the read and as soon as mosule 1 see that the
> > > read signal is pulldown he pulldown the data is ready signal.

> > > this is just one way (usually called full-handshake) and there are
> many
> > > other.

> > > have a nice day

> > >    Illan



> > > > Hi all,

> > > > For my design, there is a global clock, some input signals,  some
> > > output
> > > > signals (clocked by external source).

> > > > When input signals come in(synchronized by global clock), the
> central
> > > > controller will collect, organize, manipulate & store in buffer.
> > > > The output port interface portion will at intervals (ctrl by
> external
> > > clk)
> > > > request data from buffer.
> > > > During my design, I encounter hundreds of design warning by
> > > max+plus2 (i'm
> > > > using synplify vhdl sythesizer) saying sth like this
> > > > "Design Dr warning: flipflop or synchronous memory 'q_data_7'
> > > receives data
> > > > that is synchronized by another clock at flipflop or synchronous
> > > memory
> > > > 'subc_datareq'   "
> > > >     &
> > > > "Design Dr warning: inverting delay chain starting at primitive
> > > > 'cntr_1_lut_5'  feeds primitive 'statemachine_cntr_i_0' "

> > > > & my project fails to work during timing simulation.
> > > > Can somebody pls shed some light on how to properly design a
> multiple
> > > clock
> > > > system that meets all setup time, hold time....???
> > > > or is there any good reference that stress on this area of design?

> > > > Any help is much appreciated.  Thanks in advance.

> > > > Rgds
> > > > MK

> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Fri, 04 Oct 2002 03:00:00 GMT  
 
 [ 6 post ] 

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