Author Message

Georgia Marszalek, Public Relations Counsel

Mehdi Mohtashemi, Director of Verification Methodology

VERA 3.0 Adds new Source-Level De{*filter*} and links to Quickturn's emulators

Palo Alto, CA--July 21, 1997--Systems Science, Inc., a
developer of tools for design verification and test,
announced today a major new VERA(TM) Verification System release,
which includes a powerful source-level de{*filter*} for the VERA-HVL(TM)
(hardware verification language), and links to Quickturn's emulators.  
The VERA 3.0 release has focused on ease-of-use capabilities so that
engineers can use VERA most effectively to verify the correct operation
of blocks, ASICs, and complete systems.

VERA-HVL is a hardware verification language designed expressly for
functional validation rather than for hardware design.
The main benefit of using VERA to verify Verilog designs is that one can
create much more exhaustive and stressful test conditions with less
engineering effort than if one used a pure Verilog environment.
VERA can be used with Verilog-XL, NC-Verilog, VCS, Frontline, and
Speedsim simulators, and with Quickturn emulators.

Daniel Chapiro, Systems Science's Chairman and CEO, said,
"We are focused on providing enabling technology for verification and test
to the leading companies in the electronics industry. This new release
allows engineers to further harness the concurrent and object-oriented
capabilities of VERA to thoroughly verify their hardware faster than
it was ever possible before."

Naeem Zafar, Vice President, Marketing, Quickturn Design Systems, Inc.
added, "Four months ago we announced a joint agreement to develop a
functional verification solution for complex ICs in response to the
importance placed on both emulation and testbench tools by our customers.
Systems Science's VERA allows designers using Quickturn's emulators
to drive and sense data, just as if the circuit were running in software.
This integrated product provides an optimal combination of flexibility
and speed to help designers move their designs easily from simulation
to in-circuit emulation, shortening the verification process
and time to market."

VERA's new source-level de{*filter*} allows users to observe and
easily control the many concurrent operations that may be going on at once in
testbenches that exercise designs thoroughly. It has a flexible
graphical interface, which is based on industry-standard Tcl/Tk, which
is also compatible with standard Verilog graphical debugging environments.
Engineers can easily setup breakpoints, see the different parallel contexts,
find out about the status of different threads of execution, etc., as
they thoroughly validate the design.

Verification engineers who used the beta version said that
the new VERA de{*filter*} is helping them zoom-in on the bugs much more easily
and speed up their whole verification cycle by increasing productivity
in the debug loop.

The other major enhancement is the tight linkage with the Quickturn
System Realizer and CoBALT emulators. This interface allows design and
verification engineers to use the exact same VERA testbenches which
they used for verification with Verilog, but with an emulator instead.
Users can easily re-target their testbenches
from driving Verilog simulations to driving the same circuit running
in an emulator.

VERA 3.0 is available now on Sun and HP platforms. Unit prices for
floating licenses range from $7,500 to $27,500, depending on the options.

Systems Science, Inc. develops and markets electronic design automation,
verification, and test tools for the electronics and semiconductor industries.
The company's headquarters are located at 1860 Embarcadero Rd., Ste. 260
in Palo Alto, CA. For more information please contact us at


NOTE: Screen shot is available in electronic form.

Fri, 07 Jan 2000 03:00:00 GMT  
 [ 1 post ] 

 Relevant Pages 

1. OZ++ system released with compiler, execution system and management systems

2. NEW RELEASE: Oberon System 3, Release 2.2

3. NEW RELEASE: Oberon System 3, Release 2.2

4. Announcing Release 2.3d of the OPAL Compilation System

5. ANNOUNCE: Oberon System 3 Release 2.3.0

6. Announcing release 1.2 of the Market Analysis System

7. New Eiffel development system released

8. New release of the CAML system

9. New Eiffel development system released

10. New Oberon System 3 Release 2.1

11. New Eiffel development system released

12. New Oberon System 3 Release 2.1 - September 4.


Powered by phpBB® Forum Software